LTC3789_技术文档

LTC3862-2

Multi-Phase Current Mode

Step-Up DC/DC Controller

FeaTures

DescripTion

n

Wide V Range: 5.5V to 36V Operation

TheLTC^®3862-2isatwo-phaseconstantfrequency,current

mode boost and SEPIC controller that drives N-channel

power MOSFETs. Two-phase operation reduces system

filtering capacitance and inductance requirements.

IN

n

2-Phase Operation Reduces Input and Output

Capacitance

n

Fixed Frequency, Peak Current Mode Control

n

Internal 10V LDO Regulator

Theoperatingfrequencycanbesetwithanexternalresistor

over a 75kHz to 500kHz range and can be synchronized

to an external clock using the internal PLL. Multiphase

operation is possible using the SYNC input, the CLKOUT

output and the PHASEMODE control pin allowing 2-, 3-,

4-, 6- or 12-phase operation.

n

Lower UVLO Thresholds Allows the Use of

MOSFETs Rated at 6V V

GS

n

Adjustable Slope Compensation Gain

Adjustable Max Duty Cycle (Up to 96%)

Adjustable Leading Edge Blanking

1ꢀ Internal Voltage Reference

Other features include an internal 10V LDO with under-

voltage lockout protection for the gate drivers, a preci-

sion RUN pin threshold with programmable hysteresis,

soft-start and programmable leading edge blanking and

maximum duty cycle.

Programmable Operating Frequency with One

External Resistor (75kHz to 500kHz)

Phase-Lockable Fixed Frequency 50kHz to 650kHz

SYNC Input and CLKOUT for 2-, 3-, 4-, 6- or

12-Phase Operation (PHASEMODE Programmable)

24-Lead Narrow SSOP Package

n

+

–

PART NUMBER

LTC3862

INTV

UV

CC

5mm × 5mm QFN Package with 0.65mm Lead Pitch

24-Lead Thermally Enhanced TSSOP Package

5V

3.3V

7.5V

4.4V

2.9V

7.0V

3.9V

LTC3862-1

LTC3862-2

10V

applicaTions

L, LT, LTC, LTM, Linear Technology, the Linear logo and PolyPhase are registered trademarks

and No R and ThinSOT are trademarks of Linear Technology Corporation. All other

trademarks are the property of their respective owners. Protected by U.S. Patents, including

6144194, 6498466, 6611131.

SENSE

n

Automotive, Telecom and Industrial Power Supplies

Typical applicaTion

V

IN

6V TO 32V

22µF

50V

Efficiency vs Output Current

100k

16µH

V

OUT

V

= 80V

97

95

93

91

89

87

85

83

81

79

77

OUT

80V

V

24.9k

IN

7A (MAX)

RUN

INTV

GATE1

+

SENSE1

CC

210µF

100V

4.7µF

0.0033Ω

LTC3862-2

–

BLANK

FREQ

SYNC

SENSE1

110k

GATE2

+

SENSE2

PLLFLTR

0.1µF

V

= 6V

IN

0.0033Ω

= 9V

SS

–

= 12V

= 24V

SENSE2

1nF

3V8

PGND

CLKOUT

SLOPE

10

100

1000

10000

FB

LOAD CURRENT (mA)

10nF

D

MAX

38622 TA01b

ITH

PHASEMODE

SGND

12.1k

796k

12.4k

220pF

38622 TA01a

38622f

1

LTC3862-2

absoluTe MaxiMuM raTings ^{(Notes 1, 2)}

Input Supply Voltage (V )......................... –0.3V to 40V

SS, PLLFLTR Voltage................................ –0.3V to V

IN

3V8

INTV Voltage ..........................................–0.3V to 11V

ITH Voltage ............................................... –0.3V to 2.7V

FB Voltage.................................................. –0.3V to 3V8

FREQ Voltage............................................ –0.3V to 1.5V

Operating Junction Temperature Range (Notes 3, 4)

LTC3862-2E .........................................–40°C to 85°C

LTC3862-2I ........................................ –40°C to 125°C

LTC3862-2H....................................... –40°C to 150°C

Storage Temperature Range .................. –65°C to 150°C

Reflow Peak Body Temperature ...........................260°C

CC

INTV LDO RMS Output Current .........................50mA

CC

RUN Voltage................................................. –0.3V to 8V

SYNC Voltage............................................... –0.3V to 6V

SLOPE, PHASEMODE, D

,

MAX

BLANK Voltage .......................................... –0.3V to 3V8

+

–

+

SENSE1 , SENSE1 , SENSE2 ,

SENSE2 Voltage ...................................... –0.3V to V

3V8

pin conFiguraTion

TOP VIEW

1

2

3V8

24

23

22

21

20

19

18

17

16

15

14

13

D

MAX

1

3V8

24

23

22

21

20

19

18

17

16

15

14

13

D

MAX

+

–

SENSE1

RUN

SLOPE

BLANK

PHASEMODE

FREQ

+

–

2

3

SENSE1

RUN

SLOPE

BLANK

PHASEMODE

FREQ

3

24 23 22 21 20 19

4

BLANK

1

2

3

4

5

6

18

V

IN

4

5

V

17 INTV

PHASEMODE

IN

CC

5

V

IN

FREQ

SS

GATE1

16

6

INTV

CC

SS

6

INTV

CC

SS

25

PGND

25

PGND

15 PGND

14 GATE2

13 NC

7

GATE1

PGND

GATE2

NC

ITH

7

GATE1

PGND

GATE2

NC

ITH

FB

8

FB

8

FB

9

SGND

9

SGND

7

8

9 10 11 12

10

11

12

CLKOUT

SYNC

10

11

12

CLKOUT

SYNC

–

+

SENSE2

–

+

SENSE2

PLLFLTR

UH PACKAGE

24-LEAD (5mm × 5mm) PLASTIC QFN

FE PACKAGE

GN PACKAGE

24-LEAD NARROW PLASTIC SSOP

24-LEAD PLASTIC TSSOP

T

= 150°C, θ = 44°C/W

JA

JMAX

T

= 150°C, θ = 38°C/W

JA

EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB

JMAX

T

JMAX

= 150°C, θ = 85°C/W

JA

EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB

38622f

2

LTC3862-2

orDer inForMaTion

LEAD FREE FINISH

LTC3862EFE-2#PBF

LTC3862IFE-2#PBF

LTC3862HFE-2#PBF

LTC3862EGN-2#PBF

LTC3862IGN-2#PBF

LTC3862HGN-2#PBF

LTC3862EUH-2#PBF

LTC3862IUH-2#PBF

LTC3862HUH-2#PBF

TAPE AND REEL

PART MARKING*

LTC3862FE-2

LTC3862GN-2

38622

PACKAGE DESCRIPTION

24-Lead Plastic TSSOP

TEMPERATURE RANGE

–40°C to 85°C

LTC3862EFE-2#TRPBF

LTC3862IFE-2#TRPBF

LTC3862HFE-2#TRPBF

LTC3862EGN-2#TRPBF

LTC3862IGN-2#TRPBF

LTC3862HGN-2#TRPBF

LTC3862EUH-2#TRPBF

LTC3862IUH-2#TRPBF

LTC3862HUH-2#TRPBF

24-Lead Plastic TSSOP

–40°C to 125°C

–40°C to 150°C

–40°C to 85°C

24-Lead Plastic TSSOP

24-Lead Plastic SSOP

–40°C to 125°C

–40°C to 150°C

–40°C to 85°C

24-Lead Plastic SSOP

24-Lead (5mm × 5mm) Plastic QFN

38622

–40°C to 125°C

–40°C to 150°C

38622

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

(Notes 2, 3) The l denotes the specifications which apply over the

elecTrical characTerisTics

specified operating junction temperature range, otherwise specifications are at T_A= 25°C. V_IN= 12V, RUN = 2V and SS = open, unless

otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Supply Input and INTV Linear Regulator

CC

l

V

Supply Voltage Range

Supply Current

5.5

36

V

IN

I

VIN

l

Normal Mode, No Switching

Shutdown

(Note 5)

RUN

1.8

30

3.0

80

mA

µA

V

= 0V

INTV

LDO Regulator Output Voltage

Line Regulation

9.5

–2

10.0

10.5

0.02

V

ꢀ/V

ꢀ

CC

dV

12V < V < 36V

0.002

INTVCC(LINE)

INTVCC(LOAD)

IN

Load Regulation

Load = 0mA to 20mA

V

INTV UVLO Voltage

Rising INTV

CC

4.4

3.9

V

UVLO

CC

Falling INTV

CC

3V8

LDO Regulator Output Voltage

3.8

V

Switcher Control Loop

Reference Voltage

l

V

ITH

= 0.8V (Note 6) E-Grade (Note 3)

I-Grade and H-Grade (Note 3)

1.210

1.199

1.223

1.235

1.248

V

FB

dV /dV

Feedback Voltage V Line Regulation

V

= 5.5V to 36V (Note 6)

0.002

0.01

660

0.01

0.1

ꢀ/V

ꢀ

FB

IN

dV /dV

FB

Feedback Voltage Load Regulation

Transconductance Amplifier Gain

= 0.5V to 1.2V (Note 6)

ITH

g

m

= 0.8V (Note 6), ITH Pin Load = 5µA

µMho

MHz

f

Error Amplifier Unity-Gain Crossover

Frequency

(Note 7)

1.8

0dB

38622f

3

LTC3862-2

(Notes 2, 3) The l denotes the specifications which apply over the

elecTrical characTerisTics

specified operating junction temperature range, otherwise specifications are at T_A= 25°C. V_IN= 12V, RUN = 2V and SS = open, unless

otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

ITH

Error Amplifier Maximum Output Voltage

(Internally Clamped)

V

FB

= 1V, No Load

2.7

V

Error Amplifier Minimum Output Voltage

Error Amplifier Output Source Current

Error Amplifier Output Sink Current

Error Amplifier Input Bias Currents

V

= 1.5V, No Load

50

–30

30

mV

µA

nA

FB

I

ITH

(Note 6)

–50

–200

2

FB

V

Pulse Skip Mode Operation ITH Pin Voltage Rising ITH Voltage (Note 6)

Hysteresis

0.275

25

V

mV

ITH(PSKIP)

I

SENSE Pin Current

0.01

µA

SENSE(ON)

V

Maximum Current Sense Input Threshold

V

= Float, Low Duty Cycle

68

65

75

82

85

mV

SENSE(MAX)

SLOPE

l

(Note 3)

V

CH1 to CH2 Maximum Current Sense

Threshold Matching

V

SLOPE

= Float, Low Duty Cycle (Note 3)

–7

7

mV

SENSE(MATCH)

(V

– V

)

SENSE2

SENSE1

RUN/Soft-Start

I

RUN Source Current

V

RUN

V

RUN

= 0V

= 1.5V

–0.5

–5

µA

RUN

V

High Level RUN Channel Enable Threshold

RUN Threshold Hysteresis

SS Pull-Up Current

1.22

80

V

mV

µA

RUN

RUNHYS

I

V

= 0V

–5

SS

R

SS Pull-Down Resistance

= 0V

10

kΩ

SS

RUN

Oscillator

f

Oscillator Frequency

R

= 45.6k

280

260

300

320

340

kHz

OSC

FREQ

l

Oscillator Frequency Range

75

500

kHz

V

Nominal FREQ Pin Voltage

R

= 45.6k

1.223

FREQ

SYNC

l

f

SYNC Minimum Input Frequency

SYNC Maximum Input Frequency

SYNC Input Threshold

V

= External Clock

50

kHz

V

SYNC

650

V

Rising Threshold

1.5

–15

15

SYNC

I

Phase Detector Sourcing Output Current

Phase Detector Sinking Output Current

Channel 1 to Channel 2 Phase Relationship

f

> f

< f

µA

PLLFLTR

SYNC

OSC

CH1-CH2

V

= 0V

= Float

= 3V8

180

120

Deg

PHASEMODE

CH1-CLKOUT

Channel 1 to CLKOUT Phase Relationship

Maximum Duty Cycle

V

= 0V

90

60

Deg

PHASEMODE

= Float

= 3V8

240

D

V

DMAX

V

DMAX

V

DMAX

= 0V (Note 9)

= Float

= 3V8

96

84

75

ꢀ

MAX

38622f

4

LTC3862-2

elecTrical characTerisTics ^{(Notes 2, 3) The}l denotes the specifications which apply over the

specified operating junction temperature range, otherwise specifications are at T_A= 25°C. V_IN= 12V, RUN = 2V and SS = open, unless

otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

210

290

375

MAX

UNITS

ns

t

Minimum On-Time

V

BLANK

V

BLANK

V

BLANK

= 0V (Note 8)

= Float (Note 8)

= 3V8 (Note 8)

ON(MIN)1

ON(MIN)2

ON(MIN)3

ns

Gate Driver

R

Driver Pull-Up R

3

Ω

DS(ON)

Driver Pull-Down R

0.9

DS(ON)

Overvoltage

V

, Overvoltage Lockout Threshold

FB

V

– V in Percent

FB(NOM)

8

10

12

ꢀ

FB(OV)

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 4: This IC includes overtemperature protection that is intended to

protect the device during momentary overload conditions. Continuous

operation above the specified maximum operating junction temperature

may impair device reliability.

Note 2: All currents into device pins are positive; all currents out of device

pins are negative. All voltages are referenced to ground unless otherwise

specified.

Note 5: Supply current in normal operation is dominated by the current

needed to charge the external MOSFET gates. This current will vary with

supply voltage and the external MOSFETs used.

Note 3: The LTC3862E-2 is guaranteed to meet performance specifications

from 0°C to 85°C. Specifications over the –40°C to 85°C operating

temperature range are assured by design, characterization and correlation

with statistical process controls. The LTC3862I-2 is guaranteed over the

full –40°C to 125°C operating temperature range and the LTC3862H-2 is

guaranteed over the full –40°C to 150°C operating temperature range.

High junction temperatures degrade operating lifetimes. Operating lifetime

is derated at junction temperatures greater than 125°C.

Note 6: The IC is tested in a feedback loop that adjusts V to achieve a

specified error amplifier output voltage.

Note 7: Guaranteed by design, not subject to test.

Note 8: The minimum on-time condition is specified for an inductor peak-

to-peak ripple current = 30ꢀ (see Minimum On-Time Considerations in the

Applications Information section).

Note 9: The maximum duty cycle limit is derived from an internal

clock that runs at 12× the programmed switching frequency. See the

Applications Information section for additional information.

FB

38622f

5

LTC3862-2

Typical perForMance characTerisTics

Load Step

Inductor Current at Light Load

Efficiency vs Output Current

V

= 80V

97

95

93

91

89

87

85

83

81

79

77

I

OUT

LOAD

1A/DIV

500mA

TO 1A

SW1

50V/DIV

SW2

50V/DIV

I

LOAD1

2A/DIV

I

LOAD2

2A/DIV

I

L

1A/DIV

I

V

L

OUT

1A/DIV

1V/DIV

V

IN

V

IN

V

IN

V

IN

= 6V

= 9V

38622 G03

38622 G02

400µs/DIV

1µs/DIV

V

LOAD

= 24V

= 12V

= 24V

V

= 24V

OUT

IN

= 72V

OUT

I

= 100mA

10

100

1000

10000

LOAD CURRENT (mA)

38622 TA01b

Shutdown Quiescent Current

vs Input Voltage

Quiescent Current

vs Input Voltage

Quiescent Current vs Temperature

5.6

5.2

4.8

4.4

4.0

3.6

3.2

2.8

2.4

2.0

1.6

1.2

0.8

0.4

0

50

40

30

20

10

0

1.90

1.85

1.80

1.75

1.70

1.65

1.60

1.55

1.50

4

8

12 16 20 24 28 32 36

INPUT VOLTAGE (V)

38622 G04

4

8

12 16 20 24 28 32 36

INPUT VOLTAGE (V)

38622 G06

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

38622 G05

Shutdown Quiescent Current

vs Temperature

INTV_CCLine Regulation

INTV_CCLoad Regulation

50

40

30

20

10

0

12

10

8

10.10

10.05

10.00

9.95

V

= 12V

IN

6

4

9.90

2

50

TEMPERATURE (°C)

0

10

20

30

40

50

–50 –25

0

25

75 100 125 150

4

8

36

12 16 20 24 28 32

INPUT VOLTAGE (V)

INTV LOAD CURRENT (mA)

CC

38622 G07

38622 G08

38622 G09

38622f

6

LTC3862-2

Typical perForMance characTerisTics

INTV_CCLDO Dropout Voltage

vs Load Current, Temperature

INTV_CCUVLO Threshold

vs Temperature

INTV_CCvs Temperature

4.6

4.5

4.4

4.3

4.2

4.1

4.0

3.9

3.8

3.7

3.6

10.05

10.04

10.03

10.02

10.01

10.00

9.99

1400

1200

1000

800

600

400

200

0

RISING

150°C

125°C

85°C

25°C

FALLING

9.98

9.97

–40°C

9.96

9.95

50

–50

0

100

150

50

TEMPERATURE (°C)

–50 –25

0

25

75 100 125 150

10

0

20

30

40

50

TEMPERATURE (°C)

INTV LOAD (mA)

CC

38622 G12

38622 G10

38622 G11

Feedback Voltage Line

Regulation

Current Sense Threshold

vs ITH Voltage

Feedback Voltage vs Temperature

1.235

1.233

1.231

1.229

1.227

1.225

1.223

1.221

1.219

1.217

1.215

1.213

1.211

1.226

1.225

1.224

1.223

1.222

1.221

1.220

80

70

60

50

40

30

20

10

0

–50

0

25 50 75 100 125 150

TEMPERATURE (°C)

24

28

–25

8

12

16

20

32

36

0

0.4

0.8

1.2

1.6

2.0

2.4

INPUT VOLTAGE (V)

ITH VOLTAGE (V)

38622 G13

38622 G14

38622 G15

Current Sense Threshold

vs Temperature

Maximum Current Sense

Threshold vs Duty Cycle

RUN Threshold vs Temperature

80

75

70

65

60

55

50

45

40

35

30

80

79

78

77

76

75

74

73

72

71

70

1.30

1.25

1.20

1.15

SLOPE = 0.625

ON

SLOPE = 1.66

SLOPE = 1

OFF

1.10

0

10 20 30

40 50

60 70 100

80 90

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

–50

50

100 125

150

–25

0

25

75

DUTY CYCLE (%)

TEMPERATURE (°C)

38622 G17

38622 G18

38622 G16

38622f

7

LTC3862-2

Typical perForMance characTerisTics

RUN (Off) Source Current

vs Temperature

RUN (On) Source Current

vs Temperature

RUN Threshold vs Input Voltage

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

–0.7

–0.8

–0.9

–1.0

0

–1

–2

–3

–4

–5

–6

–7

–8

1.5

1.4

1.3

1.2

1.1

1.0

ON

OFF

50 75

TEMPERATURE (°C)

–50 –25

0

25

100 125 150

0

5

10 15 20 25 30 35 40

INPUT VOLTAGE (V)

–50 –25

0

25 50 75 100

TEMPERATURE (°C)

125

150

38622 G21

38622 G19

38622 G20

RUN Source Current

vs Input Voltage

Soft-Start Current

Soft-Start Current vs Temperature

vs Soft-Start Voltage

0

–1

–2

–3

–4

–5

–6

0

–1

–2

–3

–4

–5

–6

–5.0

–5.1

–5.2

–5.3

–5.4

–5.5

–5.6

20

INPUT VOLTAGE (V)

2.5

3

4

8

12 16

24 28 32 36

0

0.5

1

1.5

2

3.5

4

75 100

–50 –25

0

25 50

125 150

SOFT-START VOLTAGE (V)

TEMPERATURE (°C)

38622 G19

38622 G24

38622 G23

Oscillator Frequency

vs Input Voltage

Oscillator Frequency

vs Temperature

R_FREQvs Frequency

307

306

305

304

303

302

301

300

299

298

320

315

310

305

300

295

290

285

280

1000

100

10

50 75

TEMPERATURE (°C)

20 24

INPUT VOLTAGE (V)

100 200

400

300

600 700 800

1000

900

–50 –25

0

25

100 125 150

4

8

12 16

28 32 36

500

0

FREQUENCY (kHz)

38622 G27

38622 G25

38622 G26

38622f

8

LTC3862-2

Typical perForMance characTerisTics

Minimum On-Time

vs Temperature

Frequency Pin Voltage

Frequency vs PLLFLTR Voltage

vs Temperature

1400

1200

1.235

1.233

1.231

430

380

330

280

230

180

130

BLANK = 3V8

1.229

1.227

1.225

1000

800

600

400

200

0

BLANK = FLOAT

BLANK = SGND

1.223

1.221

1.219

1.217

1.215

1.213

1.211

0.5

1

1.5

2.5

0

2

50 75

TEMPERATURE (°C)

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

–50 –25

0

25

100 125 150

PLLFLTR VOLTAGE (V)

38622 G28

38622 G29

38622 G30

Minimum On-Time

vs Input Voltage

Gate Turn-On Waveform Driving

Renesas HAT2267H

Gate Turn-Off Waveform Driving

Renesas HAT2267H

430

380

330

280

230

180

130

V

GATE

2V/DIV

BLANK = 3V8

BLANK = FLOAT

BLANK = SGND

V

GATE

2V/DIV

20ns/DIV

38622 G32

38622 G33

V

I

= 24V

V

I

= 24V

IN

OUT

LOAD

IN

= 72V

= 0.25A

= 72V

OUT

24 28

12 16 20

INPUT VOLTAGE (V)

= 0.25A

4

8

32 36

LOAD

38622 G31

38622f

9

LTC3862-2

pin FuncTions

3V8: Output of the Internal 3.8V LDO from INTV . Supply

pin for the low voltage analog and digital circuits. A low

ESR 1nF ceramic bypass capacitor should be connected

between 3V8 and SGND, as close as possible to the IC.

INTV :OutputoftheInternal10VLowDropoutRegulator

CC

(LDO). A low ESR 4.7µF (X5R or better) ceramic bypass

capacitorshouldbeconnectedbetweenINTV andPGND,

CC

as close as possible to the IC.

BLANK:BlankingTime.Floatingthispinprovidesanominal

minimum on-time of 290ns. Connecting this pin to 3V8

provides a minimum on-time of 375ns, while connecting

it to SGND provides a minimum on-time of 210ns.

ITH: Error Amplifier Output. The current comparator trip

threshold increases with the ITH control voltage. The ITH

pin is also used for compensating the control loop of the

converter.

CLKOUT: Digital Output Used for Daisy-Chaining Multiple

LTC3862-2ICsinMulti-PhaseSystems.ThePHASEMODE

pinvoltagecontrolstherelationshipbetweenCH1andCH2

as well as between CH1 and CLKOUT.

PGND:PowerGround.Connectthispinclosetothesources

ofthepowerMOSFETs.PGNDshouldalsobeconnectedto

the negative terminals of V and INTV bypass capaci-

IN

CC

tors. PGND is electrically isolated from the SGND pin. The

exposed pad of the QFN and FE packages is connected to

PGND and must be soldered to PCB ground for electrical

contact and rated thermal performance.

D

: Maximum Duty Cycle. This pin programs the

MAX

maximum duty cycle. Floating this pin provides 84ꢀ

duty cycle. Connecting this pin to 3V8 provides 75ꢀ duty

cycle, while connecting it to SGND provides 96ꢀ duty

cycle. The maximum duty cycle limit is derived from an

internal clock that runs at 12× the programmed switching

PHASEMODE: The PHASEMODE pin voltage programs

the phase relationship between CH1 and CH2 rising gate

signals, as well as the phase relationship between CH1

gate signal and CLKOUT. Floating this pin or connecting

it to either 3V8, or SGND changes the phase relationship

between CH1, CH2 and CLKOUT.

frequency. As a result, the maximum duty cycle limit D

is extremely precise.

MAX

FB: Error Amplifier Input. The FB pin should be connected

through a resistive divider network to V

output voltage.

to set the

PLLFLTR: PLL Lowpass Filter Input. When synchronizing

to an external clock, this pin serves as the lowpass filter

inputforthePLL.Aseriesresistorandcapacitorconnected

fromPLLFLTRtoSGNDcompensatethePLLfeedbackloop.

OUT

FREQ: A resistor from FREQ to SGND sets the operating

frequency.

RUN: Run Control Input. A voltage above 1.22V on the pin

turns on the IC. Forcing the pin below 1.22V causes the

IC to shut down. There is a 0.5µA pull-up current for this

pin. Once the RUN pin raises above 1.22V, an additional

4.5µA pull-up current is added to the pin for program-

mable hysteresis.

GATE1, GATE2: Gate Drive Output. The LTC3862-2 pro-

vides a 10V gate drive referenced to PGND to drive a high

voltage MOSFET.

38622f

10

LTC3862-2

pin FuncTions

+

SENSE1 , SENSE2 : Positive Inputs to the Current

Comparators. The ITH pin voltage programs the current

comparator offset in order to set the peak current trip

threshold. This pin is normally connected to a sense

resistor in the source of the power MOSFET.

SS: Soft-Start Input. For soft-start operation, connecting

a capacitor from this pin to SGND will clamp the output of

the error amp. An internal 5µA current source will charge

thecapacitorandsettherateofincreaseofthepeakswitch

current of the converter.

–

SENSE1 , SENSE2 : Negative Inputs to the Current Com-

parators. This pin is normally connected to the bottom of

the sense resistor.

SYNC: PLL Synchronization Input. Applying an external

clock between 50kHz and 650kHz will cause the operating

frequencytosynchronizetotheclock.SYNCispulleddown

by a 50k internal resistor. The rising edge of the SYNC

input waveform will align with the rising edge of GATE1

in closed-loop operation.

SGND: Signal Ground. All feedback and soft-start connec-

tionsshouldreturntoSGND.Foroptimumloadregulation,

theSGNDpinshouldbekelvinconnectedtothePCBlocation

between the negative terminals of the output capacitors.

V : Main Supply Input. A low ESR ceramic capacitor

IN

should be connected between this pin and SGND.

SLOPE: This pin programs the gain of the internal slope

compensation. Floating this pin provides a normalized

slope compensation gain of 1.00. Connecting this pin

to 3V8 increases the normalized slope compensation by

66ꢀ, and connecting it to SGND decreases the normal-

ized slope compensation by 37.5ꢀ. See the Applications

Information section for more details.

38622f

11

LTC3862-2

FuncTional DiagraM

CLKOUT

SYNC

DETECT

V

IN

PLLFLTR

V

IN

C

R

IN

P

10V

LDO

C

P

INTV

CC

D

MAX

C

VCC

3V8

PHASEMODE

FREQ

3.8V

LDO

UVLO

UV

OT

L

CLK1

CLK2

3V8

VCO

OVER

TEMP

BIAS

R

FREQ

SLOPE

COMPENSATION

D

S

D

MAX

OT

V

OUT

GATE

BLANK

R1

R2

Q

+

UV

BLANK

LOGIC

M

R

SD

BLOGIC

LOGIC

BLOGIC

C

OUT

PGND

PWM LATCH

+

S

SENSE

OV

+

–

ITRIP

V TO I

R

3V8

SS

ICMP

LOOP

PSKIP

–

5µA

SENSE

C

SS

OT

UV

SD

DUPLICATE FOR

SECOND CHANNEL

R2

R1

V

FB

ITH

SD

PSKIP

OV

R

C

SGND

RUN

C

PSKIP

OV

RUN

–

EA

+

38622 FD

4.5µA

0.5µA

+

–

0.275V

1.223V

1.345V

1.22V

38622f

12

LTC3862-2

operaTion

The Control Loop

drive supply (INTV ) and one for the low voltage analog

CC

and digital control circuitry (3V8). A block diagram of this

The LTC3862-2 uses a constant frequency, peak current

mode step-up architecture with its two channels operat-

ing 180 degrees out-of-phase. During normal operation,

each external MOSFET is turned on when the clock for

that channel sets the PWM latch, and is turned off when

the main current comparator, ICMP, resets the latch. The

peak inductor current at which ICMP trips and resets the

latch is controlled by the voltage on the ITH pin, which is

the output of the error amplifier, EA. The error amplifier

power supply arrangement is shown in Figure 1.

The Gate Driver Supply LDO (INTV )

CC

The 10V output (INTV ) of the first LDO is powered from

CC

V and supplies power to the power MOSFET gate driv-

IN

ers. The INTV pin should be bypassed to PGND with a

CC

minimumof4.7μFofceramiccapacitance(X5Rorbetter),

placed as close as possible to the IC pins. If two power

MOSFETs are connected in parallel for each channel in

order to increase the output power level, or if a single

compares the output feedback signal at the V pin to the

FB

internal 1.223V reference and generates an error signal

MOSFET with a Q greater than 50nC is used, then it is

at the ITH pin. When the load current increases it causes

G

recommended that the bypass capacitance be increased

a slight decrease in V relative to the reference voltage,

FB

to a minimum of 10μF.

which causes the EA to increase the ITH voltage until the

average inductor current matches the new load current.

After the MOSFET is turned off, the inductor current flows

throughtheboostdiodeintotheoutputcapacitorandload,

until the beginning of the next clock cycle.

Anundervoltagelockout(UVLO)circuitsensestheINTV

CC

regulatoroutputinordertoprotectthepowerMOSFETsfrom

operating with inadequate gate drive. For the LTC3862-2

the rising UVLO threshold is typically 4.4V and the hys-

teresis is typically 500mV. The LTC3862-2 was optimized

Cascaded LDOs Supply Power to the Gate Driver and

Control Circuitry

for high voltage power MOSFETs with R

ratings at

DS(ON)

a V of 6V. For applications requiring logic-level power

GS

TheLTC3862-2containstwocascadedPMOSoutputstage

low dropout voltage regulators (LDOs), one for the gate

MOSFETs, please refer to the LTC3862 data sheet.

LTC3862-2

V

IN

C

IN

–

1.223V

P-CH

+

SGND

R2

R1

INTV

CC

–

+

C

1.223V

VCC

P-CH

GATE

PGND

3V8

SGND

R4

R3

3V8

ANALOG

CIRCUITS

LOGIC

C

3V8

SGND

38622 F01

NOTE: PLACE C

AND C

CAPACITORS AS CLOSE AS POSSIBLE TO DEVICE PINS

VCC

3V8

Figure 1. Cascaded LDOs Provide Gate Drive and Control Circuitry Power

38622f

13

LTC3862-2

operaTion

Inmulti-phaseapplications,alloftheFBpinsareconnected

together and all of the error amplifier output pins (ITH) are

the maximum junction temperature of the IC is never

exceeded. The junction temperature can be estimated

using the following equations:

connectedtogether.TheINTV pins,however,shouldnot

CC

beconnectedtogether. TheINTV regulatoriscapableof

CC

I

= I + Q

G(TOT)

• f

Q(TOT)

Q

sourcing current but is not capable of sinking current. As

P

DISS

= V • (I + Q

• f)

IN

Q

G(TOT)

a result, when two or more INTV regulator outputs are

CC

T = T + P

• R

TH(JA)

connectedtogether, the highestvoltage regulator supplies

all of the gate drive and control circuit current, and the

otherregulatorsareoff.Thiswouldplaceathermalburden

on the highest output voltage LDO and could cause the

maximum die temperature to be exceeded. In multi-phase

J

A

DISS

The total quiescent current (I

) consists of the static

Q(TOT)

supply current (I ) and the current required to charge

Q

the gate capacitance of the power MOSFETs. The value

of Q

should come from the plot of V vs Q in the

G(TOT)

GS G

LTC3862-2 applications, each INTV regulator output

CC

TypicalPerformanceCharacteristicssectionoftheMOSFET

should be independently bypassed to its respective PGND

data sheet. The value listed in the electrical specifications

pin as close as possible to each IC.

may be measured at a higher V , such as 15V, whereas

GS

thevalueofinterestisatthe10VINTV gatedrivevoltage.

CC

The Low Voltage Analog and Digital Supply LDO (3V8)

As an example of the required thermal analysis, consider a

2-phase boost converter with a 5.5V to 24V input voltage

range and an output voltage of 72V at 1.5A. The switching

frequency is 150kHz and the maximum ambient tempera-

ture is 70°C. The power MOSFET used for this application

The second LDO within the LTC3862-2 is powered off

of INTV and serves as the supply to the low voltage

CC

analog and digital control circuitry, as shown in Figure 1.

The output voltage of this LDO (which also has a PMOS

output device) is 3.8V. Most of the analog and digital con-

trol circuitry is powered from the internal 3V8 LDO. The

3V8 pin should be bypassed to SGND with a 1nF ceramic

capacitor (X5R or better), placed as close as possible

to the IC pins. This LDO is not intended to be used as a

supply for external circuitry.

is the Renesas HAT2267H, which has a typical R

of

DS(ON)

13mΩ at V = 10V. From the plot of V vs Q , the total

GS

G

gate charge at V = 10V is 30nC (the temperature coef-

GS

ficient of the gate charge is low). One power MOSFET is

used for each phase. For the QFN package option:

I

P

= 3mA + 2 • 30nC • 150kHz = 12mA

= 24V • 12mA = 288mW

Q(TOT)

Thermal Considerations and Package Options

DISS

The LTC3862-2 is offered in three package options. The

T = 70°C + 288mW • 34°C/W = 79.8°C

J

5mm× 5mmQFNpackage(UH24)hasathermalresistance

Inthisexample,thejunctiontemperatureriseisonly9.8°C.

Theseequationsdemonstratehowthegatechargecurrent

typically dominates the quiescent current of the IC, and

how the choice of package option and board heat sinking

can have a significant effect on the thermal performance

of the solution.

R

TH(JA)

of34°C/W,the24-pinTSSOP(FE24)packagehasa

thermalresistanceof38°C/W,andthe24-pinSSOP(GN24)

package has a thermal resistance of 85°C/W. The QFN and

TSSOP package options have a lead pitch of 0.65mm, and

the GN24 option has a lead pitch of 0.025in.

The INTV regulator can supply up to 50mA of total

CC

current. As a result, care must be taken to ensure that

38622f

14

LTC3862-2

operaTion

To prevent the maximum junction temperature from be-

ing exceeded, the input supply current to the IC should

be checked when operating in continuous mode (heavy

If the input voltage V is low enough for the INTV LDO

IN

CC

to be in dropout, then the minimum gate drive supply

voltage is:

load) at maximum V . A trade-off between the operat-

IN

V

= V

– V

INTVCC

IN(MIN) DROPOUT

ing frequency and the size of the power MOSFETs may

need to be made in order to maintain a reliable junction

temperature. Finally, it is important to verify the calcula-

tions by performing a thermal analysis of the final PCB

using an infrared camera or thermal probe. As an option,

an external regulator shown in Figure 3 can be used to

reduce the total power dissipation on the IC.

The LDO dropout voltage is a function of the total gate

drive current and the quiescent current of the IC (typically

3mA). A curve of dropout voltage vs output current for the

LDO is shown in Figure 2. The temperature coefficient of

the LDO dropout voltage is approximately 6000ppm/°C.

The total Q-current (I

) flowing in the LDO is the sum

Q(TOT)

ofthecontrollerquiescentcurrent(3mA)andthetotalgate

charge drive current.

Thermal Shutdown Protection

In the event of an overtemperature condition (external

or internal), an internal thermal monitor will shut down

the gate drivers and reset the soft-start capacitor if the

die temperature exceeds 170°C. This thermal sensor has

a hysteresis of 10°C to prevent erratic behavior at hot

temperatures. The LTC3862-2’s internal thermal sen-

sor is intended to protect the device during momentary

overtemperature conditions. Continuous operation above

the specified maximum operating junction temperature,

however, may result in device degradation.

I

= I + Q

• f

Q(TOT)

Q

G(TOT)

After the calculations have been completed, it is impor-

tant to measure the gate drive waveforms and the gate

driver supply voltage (INTV to PGND) over all operating

CC

conditions (low V , nominal V and high V , as well

IN

as from light load to full load) to ensure adequate power

MOSFET enhancement. Consult the power MOSFET data

sheet to determine the actual R

GS

the component temperatures using an infrared camera

or thermal probe.

for the measured

DS(ON)

V , and verify your thermal calculations by measuring

Operation at Low Supply Voltage

The LTC3862-2 has a minimum input voltage of 5.5V,

making it a good choice for applications that require high

1400

1200

voltage power MOSFETs with 6V R

ratings. The gate

DS(ON)

150°C

125°C

driver for the LTC3862-2 consists of PMOS pull-up and

1000

NMOS pull-down devices, allowing the full INTV voltage

CC

800

to be applied to the gates during power MOSFET switch-

85°C

ing. Nonetheless, care should be taken to determine the

600

25°C

minimum gate drive supply voltage (INTV ) in order to

CC

400

choose the optimum power MOSFETs. Important param-

–40°C

200

eters that can affect the minimum gate drive voltage are

the minimum input voltage (V

), the LDO dropout

0

IN(MIN)

10

0

20

30

40

50

voltage, the Q of the power MOSFETs, and the operating

G

INTV LOAD (mA)

CC

frequency.

38622 F02

Figure 2. INTV_CCLDO Dropout Voltage vs Current

38622f

15

LTC3862-2

operaTion

supplies. Independently biasing the INTV pin from a

Operation at High Supply Voltage

CC

separate power supply can cause one of two possible

At high input voltages, the LTC3862-2’s internal LDO

can dissipate a significant amount of power, which could

cause the maximum junction temperature to be exceeded.

Conditions such as a high operating frequency, or the use

of more than one power MOSFET per channel, could push

the junction temperature rise to high levels. If the thermal

equations above indicate too high a rise in the junction

temperature, an external bias supply can always be used

to reduce the power dissipation on the IC, as shown in

Figure 3.

failure modes during supply sequencing. If the INTV

CC

supply comes up before the V supply, high current will

IN

flow from the external INTV supply, through the body

CC

diode of the LDO PMOS device, to the input capacitor

and V pin. This high current flow could trigger a latchup

IN

condition and cause catastrophic failure of the IC.

If, however, the V supply to the IC comes up before the

IN

INTV supply, the external INTV supply will act as a

CC

loadtotheinternalLDOintheLTC3862-2, andtheLDOwill

attempt to charge the INTV output with its short-circuit

CC

For example, a 12V system rail that is available would be

more suitable than the 24V main input power rail to power

theLTC3862-2. Also, thebiaspowercanbegeneratedwith

a separate switching or LDO regulator. An example of an

LDO regulator is shown in Figure 3. The output voltage

of the LDO regulator can be set by selecting an appropri-

ate zener diode to be higher than 10V but low enough to

divide the power dissipation between LTC3862-2 and Q1

in Figure 3. The absolute maximum voltage rating of the

current. Thiswillresultinexcessivepowerdissipationand

possible thermal overload of the LTC3862-2.

Programming the Output Voltage

The output voltage is set by a resistor divider according

to the following formula:

R2

R1





V_OUT= 1.223V 1+









INTV pin is 11V.

CC

V

The external resistor divider is connected to the output

as shown in Figure 4. Resistor R1 is normally chosen so

that the output voltage error caused by the current flowing

IN

R1

out of the V pin during normal operation is negligible

FB

Q1

compared to the current in the divider. For an output volt-

age error due to the error amp input bias current of less

than 0.5ꢀ, this translates to a maximum value of R1 of

about 30k.

D1

V

IN

LTC3862-2

INTV

CC

38622 F03

C

VCC

V

OUT

Figure 3. Using the LTC3862-2 with an External Bias Supply

LTC3862-2

FB

SGND

R2

Power Supply Sequencing

R1

AsshowninFigure1, therearebodydiodesinparallelwith

the PMOS output transistors in the two LDO regulators

in the LTC3862-2. As a result, it is not possible to bias

38622 F04

Figure 4. Programming the Output Voltage

with a Resistor Divider

the INTV and V pins of the chip from separate power

CC

IN

38622f

16

LTC3862-2

operaTion

Operation of the RUN Pin

V

IN

LTC3862-2

INTERNAL 5V

The control circuitry in the LTC3862-2 is turned on and

off using the RUN pin. Pulling the RUN pin below 1.22V

forces shutdown mode and releasing it allows a 0.5μA

current source to pull this pin up, allowing a “normally

on” converter to be designed. Alternatively, the RUN pin

can be externally pulled up or driven directly by logic.

Care must be taken not to exceed the absolute maximum

rating of 8V for this pin.

0.5µA

RUN

4.5µA

+

–

BIAS AND

START-UP

CONTROL

10V

1.22V

RUN

COMPARATOR

SGND

The comparator on the RUN pin can also be used to sense

the input voltage, allowing an undervoltage detection

circuit to be designed. This is helpful in boost converter

applications where the input current can reach very high

levels at low input voltage:

38622 F05a

Figure 5a. Using the RUN Pin for a “Normally On” Converter

V

IN

LTC3862-2

I_OUT• V_OUT

I_IN=

INTERNAL 5V

V

IN

EXTERNAL

LOGIC

0.5µA

RUN

The1.22VinputthresholdoftheRUNcomparatorisderived

from a precise bandgap reference, in order to maximize

the accuracy of the undervoltage-sensing function. The

RUN comparator has 80mV built-in hysteresis. When the

voltageontheRUNpinexceeds1.22V, thecurrentsourced

into the RUN pin is switched from 0.5μA to 5μA PTAT

(proportional to absolute temperature) current. The user

can therefore program both the rising threshold and the

amount of hysteresis using the values of the resistors in

the external divider, as shown in the following equations:

CONTROL

4.5µA

+

–

BIAS AND

START-UP

CONTROL

10V

1.22V

RUN

COMPARATOR

SGND

38622 F05b

Figure 5b. On/Off Control Using External Logic





R_A

R_B

V

LTC3862-2

IN

V

_IN(ON)= 1.22V 1+

– 0.5µ•R_A

– 5µ•R_A









INTERNAL 5V

R





R_A

R_B

A

V

_IN(OFF)= 1.22V 1+





0.5µA

RUN





4.5µA

+

–

BIAS AND

START-UP

CONTROL

Several of the possible RUN pin control techniques are

illustrated in Figure 5.

10V

1.22V

B

RUN

COMPARATOR

SGND

Frequency Selection and the Phase-Locked Loop

38622 F05c

The selection of the switching frequency is a trade-off

between efficiency and component size. Low frequency

operation increases efficiency by reducing MOSFET

switchinglosses,butrequiresalargerinductorandoutput

capacitor to maintain low output ripple.

Figure 5c. Programming the Input Voltage Turn-On and Turn-Off

Thresholds Using the RUN Pin

38622f

17

LTC3862-2

operaTion

1000

100

10

TheLTC3862-2usesaconstantfrequencyarchitecturethat

can be programmed over a 75kHz to 500kHz range using

a single resistor from the FREQ pin to ground. Figure 6

illustratestherelationshipbetweentheFREQpinresistance

and the operating frequency.

The operating frequency of the LTC3862-2 can be ap-

proximated using the following formula:

–0.9255

R

FREQ

= 5.5096E9(f

)

OSC

A phase-lock loop is available on the LTC3862-2 to syn-

chronize the internal oscillator to an external clock source

connected to the SYNC pin. Connect a series RC network

from the PLLFLTR pin to SGND to compensate PLL’s

feedback loop. Typical compensation components are a

0.01μFcapacitorinserieswitha10kresistor.ThePLLFLTR

pin is both the output of the phase detector and the input

to the voltage controlled oscillator (VCO). The LTC3862-2

phase detector adjusts the voltage on the PLLFLTR pin

to align the rising edge of GATE1 to the leading edge of

the external clock signal, as shown in Figure 7. The ris-

ing edge of GATE2 will depend upon the voltage on the

PHASEMODE pin. The capture range of the LTC3862-2’s

PLL is 50kHz to 650kHz.

100 200

400

600 700 800

1000

900

0

300

500

FREQUENCY (kHz)

38622 F06

Figure 6. FREQ Pin Resistor Value vs Frequency

SYNC

10V/DIV

GATE1

20V/DIV

GATE2

20V/DIV

CLKOUT

10V/DIV

38622 F07

V

= 24V

2µs/DIV

IN

OUT

= 72V

Because the operating frequency of the LTC3862-2 can be

programmed using an external resistor, in synchronized

applications, it is recommended that the free-running fre-

quency (as defined by the external resistor) be set to the

same value as the synchronized frequency. This results in

a start-up of the IC at approximately the same frequency

as the external clock, so that when the sync signal comes

alive,nodiscontinuityattheoutputwillbeobserved.Italso

ensures that the operating frequency remains essentially

constant in the event the sync signal is lost. The SYNC

pin has an internal 50k resistor to ground.

I

= 0.5A

PHASEMODE = SGND

Figure 7. Synchronization of the LTC3862-2

to an External Clock Using the PLL

highcurrentoutput.ThePHASEMODEpinisusedtoadjust

the phase relationship between channel 1 and channel 2,

as well as the phase relationship between channel 1 and

CLKOUT, as summarized in Table 1. The phases are cal-

culated relative to the zero degrees, defined as the rising

edge of the GATE1 output. In a 6-phase application the

CLKOUTpinofthemastercontrollerconnectstotheSYNC

input of the 2nd controller and the CLKOUT pin of the 2nd

controller connects to the SYNC pin of the 3rd controller.

Using the CLKOUT and PHASEMODE Pins

in Multi-Phase Applications

The LTC3862-2 features two pins (CLKOUT and PHASE-

MODE)thatallowmultipleICstobedaisy-chainedtogether

for higher current multi-phase applications. For a 3- or

4-phasedesign,theCLKOUTsignalofthemastercontroller

is connected to the SYNC input of the slave controller in

order to synchronize additional power stages for a single

Table 1

CH-1 to CH-2

PHASE

CH-1 to CLKOUT

PHASE

PHASEMODE

SGND

APPLICATION

2-Phase, 4-Phase

6-Phase

180°

120°

90°

60°

Float

3V8

240°

3-Phase

38622f

18

LTC3862-2

operaTion

Using the LTC3862-2 Transconductance (g ) Error

MASTER

m

Amplifier in Multi-Phase Applications

FREQ

ITH

INTV

CC

ON/OFF

CONTROL

RUN

TheLTC3862-2erroramplifierisatransconductance,org

m

LTC3862-2

amplifier, meaning that it has high DC gain but high output

impedance (the output of the error amplifier is a current

proportional to the differential input voltage). This style

of error amplifier greatly eases the task of implementing

a multi-phase solution, because the amplifiers from two

or more chips can be connected in parallel. In this case

the FB pins of multiple LTC3862-2s can be connected to-

gether, as well as the ITH pins, as shown in Figure 8. The

FB

SS

V

CLKOUT

SYNC

INDIVIDUAL

OUT

INTV PINS

CC

LOCALLY

PLLFLTR PHASEMODE

SGND

DECOUPLED

ALL RUN PINS

CONNNECTED

TOGETHER

*

SLAVE

FREQ

ITH

INTV

CC

†

RUN

ALL ITH PINS

CONNECTED

TOGETHER

LTC3862-2

g of the composite error amplifier is simply n times the

†

m

FB

SS

transconductance of one amplifier, or g

= n • 660μS,

m(TOT)

CLKOUT

SYNC

where n is the number of amplifiers connected in paral-

lel. The transfer function from the ITH pin to the current

comparator inputs was carefully designed to be accurate,

both from channel-to-channel and chip-to-chip. This way

the peak inductor current matching is kept accurate.

ALL SS PINS

CONNNECTED

TOGETHER

PHASEMODE

PLLFLTR

SGND

*

SLAVE

INTV

CC

†

ITH

FB

RUN

ALL FB PINS

CONNECTED

TOGETHER

Abufferedversionoftheoutputoftheerroramplifierdeter-

minesthethresholdattheinputofthecurrentcomparator.

The ITH voltage that represents zero peak current is 0.4V

and the voltage that represents current limit is 1.2V (at

low duty cycle). During an overload condition, the output

of the error amplifier is clamped to 2.6V at low duty cycle,

in order to reduce the latency when the overload condition

terminates. A patented circuit in the LTC3862-2 is used

to recover the slope compensation signal, so that the

maximum peak inductor current is not a strong function

of the duty cycle.

LTC3862-2

†

SS

CLKOUT

SYNC

PHASEMODE

PLLFLTR

SGND

38622 F08

* R = 100Ω

†

C

= 100pF

X

Figure 8. LTC3862-2 Error Amplifier Configuration

for Multi-Phase Operation

internal, buffered ITH node (please note that the ITH pin

voltagemaynottrackthesoft-startvoltageduringthistime

period). An internal 5μA current source charges the SS

capacitor, and clamps the peak sense threshold until the

voltage on the soft-start capacitor reaches approximately

0.6V. The required amount of soft-start capacitance can

be estimated using the following equation:

In multi-phase applications that use more than one

LTC3862-2 controller, it is possible for ground currents

on the PCB to disturb the control lines between the ICs,

resulting in erratic behavior. In these applications the FB

pins should be connected to each other through 100Ω

resistorsandeachslaveFBpinshouldbedecoupledlocally

with a 100pF capacitor to ground, as shown in Figure 8.

t_SS

0.6V





C_SS= 5µA









Soft-Start

The SS pin has an internal open-drain NMOS pull-down

transistor that turns on when the RUN pin is pulled low,

The start-up of the LTC3862-2 is controlled by the volt-

age on the SS pin. An internal PNP transistor clamps the

current comparator sense threshold during soft-start,

thereby limiting the peak switch current. The base of the

PNP is connected to the SS pin and the emitter to an

when the voltage on the INTV pin is below its under-

CC

voltage lockout threshold, or during an overtemperature

condition. In multi-phase applications that use more than

38622f

19

LTC3862-2

operaTion

one LTC3862-2 chip, connect all of the SS pins together

and use one external capacitor to program the soft-start

time. In this case, the current into the soft-start capaci-

SW1

50V/DIV

SW2

50V/DIV

tor will be I = n • 5μA, where n is the number of SS

SS

pins connected together. Figure 9 illustrates the start-up

waveforms for a 2-phase LTC3862-2 application.

I

L1

500mA/DIV

I

L2

500mA/DIV

38622 F10

V

= 51V

2µs/DIV

RUN

IN

OUT

= 72V

5V/DIV

LIGHT LOAD (10mA)

V

OUT

100V/DIV

Figure 10. Light Load Switching Waveforms for

the LTC3862-2 at the Onset of Pulse-Skipping

I

L1

2A/DIV

I

an excessively large inductor would result in too much

effective slope compensation, and the converter could

become unstable. Likewise, if too small an inductor were

used,theinternalrampcompensationcouldbeinadequate

to prevent subharmonic oscillation.

L2

2A/DIV

38622 F09

V

R

= 24V

1ms/DIV

IN

OUT

L

= 72V

= 100Ω

Figure 9. Typical Start-Up Waveforms for a

Boost Converter Using the LTC3862-2

The LTC3862-2 contains a pin that allows the user to

program the slope compensation gain in order to opti-

mize performance for a wider range of inductance. With

the SLOPE pin left floating, the normalized slope gain is

1.00. Connecting the SLOPE pin to ground reduces the

normalized gain to 0.625 and connecting this pin to the

3V8 supply increases the normalized slope gain to 1.66.

Pulse-Skipping Operation at Light Load

As the load current is decreased, the controller enters

discontinuousmode(DCM).Thepeakinductorcurrentcan

be reduced until the minimum on-time of the controller

is reached. Any further decrease in the load current will

cause pulse-skipping to occur, in order to maintain output

regulation, which is normal. The minimum on-time of the

controller in this mode is approximately 210ns (with the

blanking time set to its minimum value), the majority of

which is leading edge blanking. Figure 10 illustrates the

LTC3862-2 switching waveforms at the onset of pulse-

skipping.

With the normalized slope compensation gain set to 1.00,

the design equations assume an inductor ripple current of

20ꢀ to 40ꢀ, as with previous designs. Depending upon

the application circuit, however, a normalized gain of 1.00

may not be optimum for the inductor chosen. If the ripple

currentintheinductorisgreaterthan40ꢀ, thenormalized

slope gain can be increased to 1.66 (an increase of 66ꢀ)

by connecting the SLOPE pin to the 3V8 supply. If the

inductor ripple current is less than 20ꢀ, the normalized

slope gain can be reduced to 0.625 (a decrease of 37.5ꢀ)

by connecting the SLOPE pin to SGND.

Programmable Slope Compensation

For a current mode boost regulator operating in CCM,

slope compensation must be added for duty cycles above

50ꢀ, in order to avoid subharmonic oscillation. For the

LTC3862-2, this ramp compensation is internal and user

adjustable. Having an internally fixed ramp compensation

waveform normally places some constraints on the value

of the inductor and the operating frequency. For example,

with a fixed amount of internal slope compensation, using

Tochecktheeffectivenessoftheslopecompensation,apply

a load step to the output and monitor the cycle-by-cycle

behavior of the inductor current during the leading and

trailing edges of the load current. Vary the input voltage

over its full range and check for signs of cycle-by-cycle

SW node instability or subharmonic oscillation. When the

38622f

20

LTC3862-2

operaTion

slope compensation is too low the converter can suffer

from excessive jitter or, worst case, subharmonic oscil-

lation. When excess slope compensation is applied to

the internal current sense signal, the phase margin of the

control loop suffers. Figure 11 illustrates inductor current

waveforms for a properly compensated loop.

Programmable Blanking and the Minimum On-Time

TheBLANKpinontheLTC3862-2allowstheusertoprogram

the amount of leading edge blanking at the SENSE pins.

Connecting the BLANK pin to SGND results in a minimum

on-time of 210ns, floating the pin increases this time to

290ns, and connecting the BLANK pin to the 3V8 supply

resultsinaminimumon-timeof375ns.Themajorityofthe

minimum on-time consists of this leading edge blanking,

due to the inherently low propagation delay of the current

comparator (25ns typ) and logic circuitry (10ns to 15ns).

The LTC3862-2 contains a patented circuit whereby most

of the applied slope compensation is recovered, in order

+

–

to provide a SENSE to SENSE threshold which is not

a strong function of the duty cycle. This sense threshold

is, however, a function of the programmed slope gain, as

shown in Figure 12. The data sheet typical specification of

Thepurposeofleadingedgeblankingistofilteroutnoiseon

the SENSE pins at the leading edge of the power MOSFET

turn-on. During the turn-on of the power MOSFET the gate

drive current, the discharge of any parasitic capacitance

on the SW node, the recovery of the boost diode charge,

and parasitic series inductance in the high di/dt path all

contributetoovershootandhighfrequencynoisethatcould

cause false-tripping of the current comparator. Due to the

wide range of applications the LTC3862-2 is well-suited

to, fixing one value of the internal leading edge blanking

time would have required the longest delay time to have

been used. Providing a means to program the blank time

allows users to optimize the SENSE pin filtering for each

application. Figure 13 illustrates the effectoftheprogram-

mable leading edge blank time on the minimum on-time

of a boost converter.

+

–

75mVforSENSE minusSENSE ismeasuredatanormal-

ized slope gain of 1.00 at low duty cycle. For applications

where the normalized slope gain is not 1.00, use Figure 12

to determine the correct value of the sense resistor.

I

LOAD

1A/DIV

I

L1

1A/DIV

I

L2

1A/DIV

V

OUT

2V/DIV

38622 F11

20µs/DIV

V

= 24V

IN

OUT

= 72V

Figure 11. Inductor Current Waveforms for a

Properly Compensated Control Loop

Programmable Maximum Duty Cycle

In order to maintain constant frequency and a low output

ripple voltage, a single-ended boost (or flyback or SEPIC)

converter is required to turn off the switch every cycle

for some minimum amount of time. This off-time allows

the transfer of energy from the inductor to the output

capacitor and load, and prevents excessive ripple current

and voltage. For inductor-based topologies like boost and

SEPIC converters, having a maximum duty cycle as close

as possible to 100ꢀ may be desirable, especially in low

80

75

SLOPE = 0.625

70

65

60

SLOPE = 1

55

50

SLOPE = 1.66

45

40

35

30

to high V

applications. However, for transformer-

V

IN

OUT

basedsolutions, havingamaximumdutycyclenear100ꢀ

is undesirable, due to the need for V • sec reset during the

primary switch off-time.

0

10 20 30 40 50 60 70 80 90 100

DUTY CYCLE (%)

38622 F12

Figure 12. Effect of Slope Gain on the Peak SENSE Threshold

38622f

21

LTC3862-2

operaTion

MINIMUM ON-TIME AT LIGHT LOAD WITH BLANK = SGND

96% MAXIMUM DUTY CYCLE WITH D

= SGND

MAX

INDUCTOR

CURRENT

200mA/DIV

INDUCTOR

CURRENT

1A/DIV

GATE

5V/DIV

SW NODE

20V/DIV

SW NODE

20V/DIV

500ns/DIV

V

= 36V

1µs/DIV

IN

OUT

= 72V

MEASURED ON-TIME = 210ns

MINIMUM ON-TIME AT LIGHT LOAD WITH BLANK = FLOAT

84% MAXIMUM DUTY CYCLE WITH D

= FLOAT

MAX

INDUCTOR

CURRENT

200mA/DIV

GATE

5V/DIV

SW NODE

20V/DIV

INDUCTOR

CURRENT

1A/DIV

SW NODE

20V/DIV

V

= 36V

500ns/DIV

1µs/DIV

IN

OUT

= 72V

MEASURED ON-TIME = 290ns

MINIMUM ON-TIME AT LIGHT LOAD WITH BLANK = 3V8

75% MAXIMUM DUTY CYCLE WITH D

= 3V8

MAX

INDUCTOR

CURRENT

200mA/DIV

GATE

5V/DIV

SW NODE

20V/DIV

INDUCTOR

CURRENT

1A/DIV

SW NODE

20V/DIV

38622 F13

38622 F14

V

= 36V

500ns/DIV

IN

OUT

1µs/DIV

= 72V

MEASURED ON-TIME = 375ns

Figure 14. SW Node Waveforms with Different Duty Cycle Limits

Figure 13. Leading Edge Blanking Effects

on the Minimum On-Time

In order to satisfy these different applications require-

ments, the LTC3862-2 has a simple way to program the

The LTC3862-2 contains an oscillator that runs at 12× the

programmed switching frequency, in order to provide for

2-, 3-, 4-, 6- and 12-phase operation. A digital counter is

usedtodividedownthefundamentaloscillatorfrequencyin

ordertoobtaintheoperatingfrequencyofthegatedrivers.

Since the maximum duty cycle limit is obtained from

thisdigitalcounter, thepercentagemaximumdutycycle

does not vary with process tolerances or temperature.

maximum duty cycle. Connecting the D

pin to SGND

MAX

limits the maximum duty cycle to 96ꢀ. Floating this pin

limits the duty cycle to 84ꢀ and connecting the D pin

MAX

to the 3V8 supply limits it to 75ꢀ. Figure 14 illustrates

the effect of limiting the maximum duty cycle on the SW

node waveform of a boost converter.

38622f

22

LTC3862-2

operaTion

The SENSE and SENSE Pins

+

–

adjacent to the negative terminal of the output capacitor,

since this path is a part of the high di/dt loop formed by

the switch, boost diode, output capacitor and sense resis-

tor. Placement of the inductors is less critical, since the

current in the inductors is a triangle waveform.

+

–

The SENSE and SENSE pins are high impedance inputs

to the CMOS current comparators for each channel.

Nominally, there is no DC current into or out of these

pins. There are ESD protection diodes connected from

these pins to SGND, although even at hot temperature the

Checking the Load Transient Response

+

–

leakage current into the SENSE and SENSE pins should

be less than 1μA.

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

Since the LTC3862-2 contains leading edge blanking, an

external RC filter is not required for proper operation.

However, if an external filter is used, the filter components

load current. When a load step occurs, V

shifts by an

OUT

amount equal to ∆I

(ESR), where ESR is the effective

LOAD

+

–

should be placed close to the SENSE and SENSE pins on

the IC, as shown in Figure 15. The positive and negative

sense node traces should then run parallel to each other

to a Kelvin connection underneath the sense resistor, as

shown in Figure 16. Sensing current elsewhere on the

board can add parasitic inductance and capacitance to

the current sense element, degrading the information at

the sense pins and making the programmed current limit

series resistance of C . ∆I

also begins to charge or

OUT

LOAD

discharge C , generating the feedback error signal that

OUT

forces the regulator to adapt to the current change and

return V

to its steady-state value. During this recovery

can be monitored for excessive overshoot or

OUT

time V

OUT

ringing, which would indicate a stability problem.

The availability of the ITH pin not only allows optimization

of control loop behavior but also provides a DC-coupled

and AC-filtered closed-loop response test point. The DC

step,risetimeandsettlingatthistestpointtrulyreflectsthe

closed-loop response. Assuming apredominantly second

ordersystem, phasemarginand/ordampingfactorcanbe

estimated using the percentage of overshoot seen at this

pin. The bandwidth can also be estimated by examining

the rise time at the pin.

–

unpredictable.AvoidthetemptationtoconnecttheSENSE

line to the ground plane using a PCB via; this could result

in unpredictable behavior.

The sense resistor should be connected to the source

of the power MOSFET and the ground node using short,

wide PCB traces, as shown in Figure 16. Ideally, the bot-

tom terminal of the sense resistors will be immediately

V

IN

V

IN

MOSFET SOURCE

INTV

CC

LTC3862-2

GATE

V

OUT

+

SENSE

R

SENSE

R

SENSE

–

SENSE

TO SENSE

FILTER NEXT

TO CONTROLLER

38622 F15

PGND

38622 F16

FILTER COMPONENTS

PLACED NEAR

SENSE PINS

GND

Figure 15. Proper Current Sense Filter Component Placement

Figure 16. Connecting the SENSE⁺and SENSE^–Traces to the

Sense Resistor Using a Kelvin Connection

38622f

23

LTC3862-2

operaTion

The ITH series R • C filter sets the dominant pole-zero

the gate with an appropriate signal generator is a practi-

cal way to produce a fast load step condition. The initial

output voltage step resulting from the step change in the

output current may not be within the bandwidth of the

feedback loop, so this signal cannot be used to determine

phase margin. This is why it is better to look at the ITH

pin signal which is in the feedback loop and is the filtered

and compensated control loop response. The gain of the

C

loop compensation. The transfer function for boost and

flyback converters contains a right half plane zero that

normally requires the loop crossover frequency to be

reduced significantly in order to maintain good phase

margin. The R • C filter values can typically be modified

C

slightly (from 0.5 to 2 times their suggested values) to

optimizetransientresponseoncethefinalPClayoutisdone

and the particular output capacitor type(s) and value(s)

havebeendetermined. Theoutputcapacitorconfiguration

needs to be selected in advance because the effective ESR

and bulk capacitance have a significant effect on the loop

gain and phase. An output current pulse of 20ꢀ to 80ꢀ

of full-load current having a rise time of 1μs to 10μs will

produce output voltage and ITH pin waveforms that will

give a sense of the overall loop stability without breaking

the feedback loop. Placing a power MOSFET and load

resistor directly across the output capacitor and driving

loop will be increased by increasing R and the bandwidth

C

of the loop will be increased by decreasing C . If R is

C

increased by the same factor that C is decreased, the

C

zero frequency will be kept the same, thereby keeping the

phase shift the same in the most critical frequency range

of the feedback loop. The output voltage settling behavior

is related to the stability of the closed-loop system and

will demonstrate the actual overall supply performance.

Figure 17 illustrates the load step response of a properly

compensated boost converter.

I

LOAD

1A/DIV

500mA TO 1A

I

L1

2A/DIV

I

L2

2A/DIV

V

OUT

1V/DIV

38622 F17

400µs/DIV

V

= 24V

IN

OUT

= 72V

Figure 17. Load Step Response of a Properly

Compensated Boost Converter

38622f

24

LTC3862-2

applicaTions inForMaTion

Typical Boost Applications Circuit

Minimum On-Time Limitations

A basic 2-phase, single output LTC3862-2 application

circuit is shown in Figure 18. External component selec-

tion is driven by the characteristics of the load and the

input supply.

In a single-ended boost converter, two steady-state condi-

tions can result in operation at the minimum on-time of

the controller. The first condition is when the input voltage

is close to the output voltage. When V approaches V

IN

OUT

the voltage across the inductor approaches zero during

the switch off-time. Under this operating condition the

converter can become unstable and the output can experi-

ence high ripple voltage oscillation at audible frequencies.

For applications where the input voltage can approach

or exceed the output voltage, consider using a SEPIC or

buck-boost topology instead of a boost converter.

Duty Cycle Considerations

For a boost converter operating in a continuous conduc-

tion mode (CCM), the duty cycle of the main switch is:



_IN

V_O+ V_F– V

D =

= t_ON• f





V_O+ V_F





The second condition that can result in operation at the

minimum on-time of the controller is at light load, in deep

discontinuous mode. As the load current is decreased,

the on-time of the switch decreases, until the minimum

on-time limit of the controller is reached. Any further de-

crease in the output current will result in pulse-skipping,

a typically benign condition where cycles are skipped in

order to maintain output regulation.

where V is the forward voltage of the boost diode. The

F

minimum on-time for a given application operating in

CCM is:

V + V – V

_IN(MAX)



1

f

F

O

t_ON(MIN)

=





V_O+ V_F





For a given input voltage range and output voltage, it is

important to know how close the minimum on-time of the

application comes to the minimum on-time of the control

IC. TheLTC3862-2minimumon-timecanbeprogrammed

from 210ns to 375ns using the BLANK pin.

V

IN

L1

19µH

D1

PDS760

8.5V TO 36V

PA2050-193

1nF

Q1

D

3V8

+

MAX

HAT2279H

10Ω

SENSE1

SLOPE

BLANK

0.005Ω

10nF

100µF

1W

63V

–

+

PHASEMODE

FREQ

SENSE1

RUN

66.5k

0.1µF

24.9k

6.8µF 50V

V

150k

OUT

6.8µF 50V

48V

1µF

SS

3A TO 5A

6.8µF 50V

10nF

LTC3862-2

100µF

63V

6.8µF 50V

V

IN

39.2k

ITH

FB

100pF

4.7µF

6.8µF 50V

0.005Ω

1W

INTV

CC

12.4k

475k

10Ω

GATE1

PGND

SGND

Q2

V

OUT

GATE2

HAT2279H

–

CLKOUT

SYNC

SENSE2

10nF

L2

19µH

PA2050-193

D2

+

PDS760

PLLFLTR

SENSE2

38622 F18

Figure 18. A Typical 2-Phase, Single Output Boost Converter Application Circuit

38622f

25

LTC3862-2

applicaTions inForMaTion

Maximum Duty Cycle Limitations

properly. Based on the fact that, ideally, the output power

is equal to the input power, the maximum average input

current is:

Another operating extreme occurs at high duty cycle,

when the input voltage is low and the output voltage is

high. In this case:

I_O(MAX)

I_IN(MAX)

=

1–D_MAX

V + V – V

_IN(MIN)



F

O

D_MAX

=





V_O+ V_F





The peak current in each inductor is:

I_O(MAX)

Asingle-endedboostconverterneedsaminimumoff-time

everycycleinordertoallowenergytransferfromtheinput

inductor to the output capacitor. This minimum off-time

translates to a maximum duty cycle for the converter. The

equation above can be rearranged to obtain the maximum

output voltage for a given minimum input or maximum

duty cycle.

1

n

χ

2





I_IN(PK)= • 1+

•









1–D_MAX

wherenrepresentsthenumberofphasesandχ represents

the percentage peak-to-peak ripple current in the inductor.

For example, if the design goal is to have 30ꢀ ripple cur-

rent in the inductor, then χ = 0.30, and the peak current

is 15ꢀ greater than the average.

V

IN

V_O(MAX)

=

– V

F

1–D_MAX

Inductor Selection

The equation for D

above can be used as an initial

Given an input voltage range, operating frequency and

ripple current, the inductor value can be determined using

the following equation:

MAX

guideline for determining the maximum duty cycle of

the application circuit. However, losses in the inductor,

input and output capacitors, the power MOSFETs, the

sense resistors and the controller (gate drive losses) all

contribute to an increasing of the duty cycle. The effect

of these losses will be to decrease the maximum output

voltage for a given minimum input voltage.

V

L = ^IN(MIN)•D_MAX

∆I_L• f

where:

I_O(MAX)

χ

After the initial calculations have been completed for an

application circuit, it is important to build a prototype of

the circuit and measure it over the entire input voltage

range, from light load to full load, and over temperature,

in order to verify proper operation of the circuit.

∆I_L=

•

n 1–D_MAX

Choosing a larger value of ∆I allows the use of a lower

L

value inductor but results in higher output voltage ripple,

greater core losses, and higher ripple current ratings for

the input and output capacitors. A reasonable starting

point is 30ꢀ ripple current in the inductor (χ = 0.3), or:

Peak and Average Input Currents

The control circuit in the LTC3862-2 measures the input

current (by means of resistors in the sources of the power

MOSFETs),sotheoutputcurrentneedstobereflectedback

to the input in order to dimension the power MOSFETs

I_O(MAX)

0.3

n

∆I_L=

•

1–D_MAX

38622f

26

LTC3862-2

applicaTions inForMaTion

The inductor saturation current rating needs to be higher

than the worst-case peak inductor current during an

current I

TH(JC)

, and thermal resistances R

and

TH(JA)

D(MAX)

R

—both junction-to-ambient and junction-to-case.

overload condition. If I

is the maximum rated load

O(MAX)

The gate driver for the LTC3862-2 consists of PMOS pull-

up and NMOS pull-down devices, allowing the full INTV

current, then the maximum current limit value (I

)

O(CL)

CC

would normally be chosen to be some factor (e.g., 30ꢀ)

greater than I

voltage to be applied to the gates during power MOSFET

switching. Nonetheless, care must be taken to ensure

that the minimum gate drive voltage is still sufficient to

full enhance the power MOSFET. Check the MOSFET data

.

O(MAX)

I

= 1.3 • I

O(MAX)

O(CL)

Reflecting this back to the input, where the current is be-

ing measured, and accounting for the ripple current, gives

a minimum saturation current rating for the inductor of:

sheet carefully to verify that the R

of the MOSFET

DS(ON)

is specified for a voltage less than or equal to the nominal

INTV voltageof10V.Forapplicationsthatrequireapower

CC

1.3 •I_O(MAX)

1

n

χ

2

MOSFETratedat5V,pleaserefertotheLTC3862datasheet.





I_L(SAT)≥ • 1+

•









1–D_MAX

Also pay close attention to the BV

specifications for

DSS

the MOSFETs relative to the maximum actual switch volt-

age in the application. Check the switching waveforms of

the MOSFET directly on the drain terminal using a single

probe and a high bandwidth oscilloscope. Ensure that the

The saturation current rating for the inductor should be

determined at the minimum input voltage (which results

in the highest duty cycle and maximum input current),

maximum output current and the maximum expected

core temperature. The saturation current ratings for most

commerciallyavailableinductorsdropathightemperature.

To verify safe operation, it is a good idea to characterize

the inductor’s core/winding temperature under the fol-

lowing conditions: 1) worst-case operating conditions,

2) maximum allowable ambient temperature and 3) with

the power supply mounted in the final enclosure. Thermal

characterization can be done by placing a thermocouple

in intimate contact with the winding/core structure, or by

buryingthethermocouplewithinthewindingsthemselves.

drain voltage ringing does not approach the BV

of the

DSS

MOSFET. Excessive ringing at high frequency is normally

an indicator of too much series inductance in the high di/

dt current path that includes the MOSFET, the boost diode,

the output capacitor, the sense resistor and the PCB traces

connecting these components.

Finally, check the MOSFET manufacturer’s data sheet for

an avalanche energy rating (EAS). Some MOSFETs are not

rated for body diode avalanche and will fail catastrophi-

cally if the V exceeds the device BV , even if only by

DS

DSS

a fraction of a volt. Avalanche-rated MOSFETs are better

Remember that a single-ended boost converter is not

short-circuit protected, and that under a shorted output

condition, the output current is limited only by the input

supply capability. For applications requiring a step-up

converter that is short-circuit protected, consider using

a SEPIC or forward converter topology.

abletosustainhighfrequencydrain-to-sourceringingnear

the device BV

during the turn-off transition.

DSS

Calculating Power MOSFET Switching and Conduction

Losses and Junction Temperatures

In order to calculate the junction temperature of the power

MOSFET,thepowerdissipatedbythedevicemustbeknown.

This power dissipation is a function of the duty cycle, the

load current and the junction temperature itself (due to

Power MOSFET Selection

The peak-to-peak gate drive level is set by the INTV

CC

voltage is 10V for the LTC3862-2 under normal operat-

the positive temperature coefficient of its R

). As a

DS(ON)

ing conditions. Selection criteria for the power MOSFETs

result, some iterative calculation is normally required to

determine a reasonably accurate value.

include the R

, gate charge Q , drain-to-source

G

DS(ON)

breakdown voltage BV , maximum continuous drain

DSS

38622f

27

LTC3862-2

applicaTions inForMaTion

The power dissipated by the MOSFET in a multi-phase

boost converter with n phases is:

The R

to be used in this equation normally includes

TH(JA)

the R

for the device plus the thermal resistance from

TH(JC)

the case to the ambient temperature (R

). This value

TH(CA)



I_O(MAX) ²

of T can then be compared to the original, assumed value

J

P_FET

=

•R_DS(ON)•D_MAX• ρ_T





used in the iterative calculation process.

n • 1–D

(

)





MAX

It is tempting to choose a power MOSFET with a very low

I_O(MAX)

+ k • V²•

•C_RSS• f

R

in order to reduce conduction losses. In doing

^OUTn • 1–D

DS(ON)

(

)

MAX

so, however, the gate charge Q is usually significantly

G

higher, which increases switching and gate drive losses.

Since the switching losses increase with the square of

the output voltage, applications with a low output voltage

generally have higher MOSFET conduction losses, and

high output voltage applications generally have higher

MOSFET switching losses. At high output voltages, the

highest efficiency is usually obtained by using a MOSFET

2

The first term in the equation above represents the I R

losses in the device, and the second term, the switching

losses.Theconstant,k=1.7,isanempiricalfactorinversely

related to the gate drive current and has the dimension

of 1/current.

The ρ term accounts for the temperature coefficient of

T

with a higher R

and lower Q . The equation above

DS(ON)

G

the R

of the MOSFET, which is typically 0.4ꢀ/ºC.

DS(ON)

can easily be split into two components (conduction and

switching) and entered into a spreadsheet, in order to

compare the performance of different MOSFETs.

Figure 19 illustrates the variation of normalized R

over temperature for a typical power MOSFET.

DS(ON)

From a known power dissipated in the power MOSFET, its

junction temperature can be obtained using the following

formula:

Programming the Current Limit

The peak sense voltage threshold for the LTC3862-2 is

75mVatlowdutycycleandwithanormalizedslopegainof

T = T + P • R

J

A

FET

TH(JA)

+

–

1.00, and is measured from SENSE to SENSE . Figure 20

illustrates the change in the sense threshold with varying

duty cycle and slope gain.

2.0

1.5

1.0

0.5

0

80

75

SLOPE = 0.625

70

65

60

SLOPE = 1

55

50

SLOPE = 1.66

45

40

35

30

50

100

0

10 20 30 40 50 60 70 80 90 100

DUTY CYCLE (%)

–50

150

0

JUNCTION TEMPERATURE (°C)

38622 F20

38622 F19

Figure 19. Normalized Power MOSFET R_DS(ON)vs Temperature

Figure 20. Maximum Sense Voltage Variation

with Duty Cycle and Slope Gain

38622f

28

LTC3862-2

applicaTions inForMaTion

For a boost converter where the current limit value is

chosen to be 30ꢀ higher than the maximum load current,

the peak current in the MOSFET and sense resistor is:

The resistor temperature can be calculated using the

equation:

T = T + P

• R

TH(JA)

D

A

R(SENSE)

1.3 •I_O(MAX)

1

n

χ

2





I_SW(MAX)= I_R(SENSE)= • 1+

•







Selecting the Output Diodes



1–D_MAX

To maximize efficiency, a fast switching diode with low

forward drop and low reverse leakage is required. The

output diode in a boost converter conducts current during

theswitchoff-time.Thepeakreversevoltagethatthediode

must withstand is equal to the regulator output voltage.

The average forward current in normal operation is equal

to the output current, and the peak current is equal to the

peak inductor current:

The sense resistor value is then:

V_SENSE(MAX)•n • 1–D

(

)

MAX

R_SENSE

=

χ

2



1.3 • 1+







•I_O(MAX)

Again, the factor n is the number of phases used, and χ

represents the percentage ripple current in the inductor.

The number 1.3 represents the factor by which the cur-

I_O(MAX)

1

χ





I_D(PEAK)= • 1+

•









n

2

1–D_MAX

rent limit exceeds the maximum load current, I

.

O(MAX)

For example, if the current limit needs to exceed the

maximum load current by 50ꢀ, then the 1.3 factor should

be replaced with 1.5.

Although the average diode current is equal to the output

current, in very high duty cycle applications (low V_INto

high V_OUT) the peak diode current can be several times

higher than the average, as shown in Figure 21. In this

case check the diode manufacturer’s data sheet to ensure

that its peak current rating exceeds the peak current in

the equation above. In addition, when calculating the

power dissipation in the diode, use the value of the for-

ward voltage (V_F) measured at the peak current, not the

average output current. Excess power will be dissipated

in the series resistance of the diode, which would not be

accounted for if the average output current and forward

voltage were used in the equations. Finally, this additional

The average power dissipated in the sense resistor can

easily be calculated as:

 1.3 •I_O(MAX) ²

P_R(SENSE)

=

•R_SENSE•D_MAX





n • 1–D

(

)





MAX

This equation assumes no temperature coefficient for

the sense resistor. If the resistor chosen has a significant

temperature coefficient, then substitute the worst-case

high resistance value into the equation.

SW NODE

50V/DIV

INDUCTOR

CURRENT

1A/DIV

DIODE

CURRENT

1A/DIV

38622 F21

V

= 12V

1µs/DIV

IN

OUT

= 72V

Figure 21. Diode Current Waveform for a High Duty Cycle Application

38622f

29

LTC3862-2

applicaTions inForMaTion

power dissipation is important when deciding on a diode

current rating, package type, and method of heat sinking.

ripple waveform are illustrated in Figure 22 for a typical

boost converter.

To a close approximation, the power dissipated by the

diode is:

The choice of component(s) begins with the maximum

acceptable ripple voltage (expressed as a percentage of

the output voltage), and how this ripple should be divided

between the ESR step and the charging/discharging ∆V.

For the purpose of simplicity we will choose 2ꢀ for the

maximum output ripple, to be divided equally between the

ESRstepandthecharging/discharging∆V.Thispercentage

ripple will change, depending on the requirements of the

application, and the equations provided below can easily

be modified.

P = I

D

• V

• (1 – D

)

D(PEAK)

F(PEAK)

MAX

The diode junction temperature is:

T = T + P • R

J

A

D

TH(JA)

The R

to be used in this equation normally includes

TH(JA)

the R

for the device plus the thermal resistance from

TH(JC)

the board to the ambient temperature in the enclosure.

Once the proper diode has been selected and the circuit

performance has been verified, measure the temperature

ofthepowercomponentsusingathermalprobeorinfrared

camera over all operating conditions to ensure a good

thermal design.

Oneofthekeybenefitsofmulti-phaseoperationisareduc-

tion in the peak current supplied to the output capacitor

by the boost diodes. As a result, the ESR requirement

of the capacitor is relaxed. For a 1ꢀ contribution to the

total ripple voltage, the ESR of the output capacitor can

be determined using the following equation:

Finally, remember to keep the diode lead lengths short

and to observe proper switch-node layout (see Board

LayoutChecklist)toavoidexcessiveringingandincreased

dissipation.

0.01• V_OUT

I_D(PEAK)

ESR_COUT

where:

I_D(PEAK)= • 1+

≤

Output Capacitor Selection

I_O(MAX)

Contributions of ESR (equivalent series resistance), ESL

(equivalent series inductance) and the bulk capacitance

mustbeconsideredwhenchoosingthecorrectcombination

of output capacitors for a boost converter application. The

effects of these three parameters on the output voltage

1

n

χ

2





•









1–D_MAX

The factor n represents the number of phases and the

factorχ representsthepercentageinductorripplecurrent.

SW1

100V/DIV

SW2

100V/DIV

I

L1

2A/DIV

I

L2

2A/DIV

V

OUT

100mV/DIV

AC COUPLED

38622 F22

1µs/DIV

V

= 24V

IN

OUT

= 72V

350mA LOAD

Figure 22. Switching Waveforms for a Boost Converter

38622f

30

LTC3862-2

applicaTions inForMaTion

For the bulk capacitance, which we assume contributes

1ꢀ to the total output ripple, the minimum required ca-

pacitance is approximately:

The output ripple current is divided between the various

capacitors connected in parallel at the output voltage.

Although ceramic capacitors are generally known for low

ESR (especially X5R and X7R), these capacitors suffer

from a relatively high voltage coefficient. Therefore, it is

not safe to assume that the entire ripple current flows in

theceramiccapacitor.Aluminumelectrolyticcapacitorsare

generally chosen because of their high bulk capacitance,

but they have a relatively high ESR. As a result, some

amount of ripple current will flow in this capacitor. If the

ripple current flowing into a capacitor exceeds its RMS

rating, the capacitor will heat up, reducing its effective

capacitance and adversely affecting its reliability. After

the output capacitor configuration has been determined

using the equations provided, measure the individual ca-

pacitor case temperatures in order to verify good thermal

performance.

I_O(MAX)

C_OUT

≥

0.01•n • V_OUT• f

For many designs it will be necessary to use one type of

capacitor to obtain the required ESR, and another type

to satisfy the bulk capacitance. For example, using a

low ESR ceramic capacitor can minimize the ESR step,

while an electrolytic capacitor can be used to supply the

required bulk C.

The voltage rating of the output capacitor must be greater

than the maximum output voltage, with sufficient derating

to account for the maximum capacitor temperature.

Because the ripple current in the output capacitor is a

square wave, the ripple current requirements for this ca-

pacitor depend on the duty cycle, the number of phases

and the maximum output current. Figure 23 illustrates the

normalized output capacitor ripple current as a function of

duty cycle. In order to choose a ripple current rating for

the output capacitor, first establish the duty cycle range,

based on the output voltage and range of input voltage.

Referring to Figure 23, choose the worst-case high nor-

malized ripple current, as a percentage of the maximum

load current.

Input Capacitor Selection

The input capacitor voltage rating in a boost converter

should comfortably exceed the maximum input voltage.

Although ceramic capacitors can be relatively tolerant of

overvoltage conditions, aluminum electrolytic capacitors

are not. Be sure to characterize the input voltage for any

possible overvoltage transients that could apply excess

stress to the input capacitors.

3.25

3.00

2.75

2.50

2.25

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0

1-PHASE

2-PHASE

0.4 0.5

0.1 0.2 0.3

0.6 0.7 0.8 0.9

DUTY CYCLE OR (1-V /V

)

IN OUT

38622 F23

Figure 23. Normalized Output Capacitor

Ripple Current (RMS) for a Boost Converter

38622f

31

LTC3862-2

applicaTions inForMaTion

The value of the input capacitor is a function of the

source impedance, and in general, the higher the source

impedance, the higher the required input capacitance.

The required amount of input capacitance is also greatly

affected by the duty cycle. High output current applica-

tions that also experience high duty cycles can place great

demands on the input supply, both in terms of DC current

and ripple current.

A Design Example

Consider the LTC3862-2 application circuit is shown in

Figure25a. Theoutputvoltageis72Vandtheinputvoltage

range is 8.5V to 36V. The maximum output current is 1.5A

when the input voltage is 24V and 2A at an input of 32V.

Below 32V, current limit will linearly reduce the maximum

load to 0.5A at 8.5V input voltage (see Figure 25b).

1. The duty cycle range (where 1.5A is available at the

output) is:

The input ripple current in a multi-phase boost converter

isrelativelylow(comparedwiththe outputripplecurrent),

because this current is continuous and is being divided

between two or more inductors. Nonetheless, significant

stress can be placed on the input capacitor, especially

in high duty cycle applications. Figure 24 illustrates the

normalized input ripple current, where:





V + V – V

F

IN

O

D

=

MAX

MIN





V + V





F

O

72V + 0.5V – 24V

72V + 0.5V





= 66.9ꢀ

= 50.3ꢀ









72V + 0.5V – 36V

72V + 0.5V





V

L • f

IN

D

=





I_NORM

=





1.00

2. The operating frequency is chosen to be 300kHz so

the period is 3.33μs. From Figure 6, the resistor from

the FREQ pin to ground is 45.3k.

0.90

0.80

0.70

0.60

0.50

0.40

0.30

0.20

0.10

0

1-PHASE

3. The minimum on-time for this application operating

in CCM is:

2-PHASE

V + V – V

_IN(MAX)



1

f

1

F

O

t_ON(MIN)= •

=

•





V_O+ V_F

300kHz





72V + 0.5V – 36V

72V + 0.5V





0

0.2

0.4

0.6

0.8

1.0

= 1.678µs









DUTY CYCLE

38622 F24

Figure 24. Normalized Input Peak-to-Peak Ripple Current

The maximum DC input current is:

I_O(MAX)

1.5A

1–D_MAX1– 0.669

I_IN(MAX)

=

= 4.5A

38622f

32

LTC3862-2

applicaTions inForMaTion

V

IN

L1

D1

8.5V TO 36V

58µH

MURS320T3H

PA2050-583

1nF

Q1

D

3V8

+

MAX

HAT2267H

10Ω

SENSE1

SLOPE

BLANK

0.020Ω

1W

10nF

47µF

100V

–

+

PHASEMODE

FREQ

SENSE1

RUN

45.3k

0.1µF

24.9k

6.8µF 50V

150k

6.8µF 50V

V

OUT

SS

1µF

72V

6.8µF 50V

2A (MAX)

47µF

100V

LTC3862-2

1.5nF

V

IN

45.3k

ITH

FB

4.7µF

100pF

2.2µF

100V

×6

INTV

CC

0.020Ω

1W

5.62k

GATE1

PGND

10Ω

SGND

324k

Q2

GATE2

SENSE2

V

OUT

HAT2267H

–

CLKOUT

SYNC

10nF

L2

D2

58µH

+

MURS320T3H

PLLFLTR

SENSE2

PA2050-583

38622 F25a

Figure 25a. A 8.5V to 36V Input, 72V/2A Output 2-Phase Boost Converter Application Circuit

2.5

2.0

1.5

1.0

0.5

0

5. The inductor ripple current is:

I_O(MAX)

χ

0.4

2

1.5A

1– 0.669

∆I_L=

•

=

•

= 0.9A

n 1–D_MAX

6. The inductor value is therefore:

V

24V

IN(MIN)

L =

•D_MAX

=

• 0.669

∆I_L• f

= 59.5µH

0.9A • 300kHz

0

10

20

30

40

INPUT VOLTAGE (V)

38622 F25b

7. Foracurrentlimitvalue30ꢀhigherthanthemaximum

load current:

Figure 25b. Output Current vs Input Voltage

I

= 1.3 • I

= 1.3 • 1.5A = 1.95A

O(CL)

O(MAX)

4. A ripple current of 40ꢀ is chosen so the peak current

in each inductor is:

The saturation current rating of the inductors must

therefore exceed:

I_O(MAX)

1

n

χ

2





I

= • 1–

•

1.3 •I_O(MAX)







1

n

χ

2

IN(PK)









1–D_MAX

I_L(SAT)≥ • 1+

•











1–D_MAX

1

0.4

2

1.5A

•



= • 1+

= 2.7A

1

0.4 1.3 •1.5A











2

1– 0.669

= • 1+

•

= 3.5A









1– 0.669

2

38622f

33

LTC3862-2

applicaTions inForMaTion

12. The power dissipated in the sense resistors in current

limit is:

The inductor value chosen was 57.8μH and the part

number is PA2050-583, manufactured by Pulse Engi-

neering. This inductor has a saturation current rating

of 5A.

 1.3 •I_O(MAX) ²

P

=

•R_SENSE•D_MAX

• 0.020 • 0.669

R(SENSE)





n • 1–D

(

)





MAX

8. The power MOSFET chosen for this application is

a Renesas HAT2267H. This MOSFET has a typical



 ²

1.3 •1.5

2 • 1– 0.669

R

of 13mΩ at V = 10V. The BV

is rated

=

DS(ON)

GS

DSS





(

)





at a minimum of 80V and the maximum continuous

drain current is 25A. The typical gate charge is 30nC

= 0.12W

for a V = 10V. Last but not least, this MOSFET has

GS

an absolute maximum avalanche energy rating EAS

of 30mJ, indicating that it is capable of avalanche

without catastrophic failure.

13. The average current in the boost diodes is half the

output current (1.5A/2 = 0.75A), but the peak current

in each diode is:

9. The total IC quiescent current, IC power dissipation

andmaximumjunctiontemperatureareapproximately:

I_O(MAX)

1

n

χ

2





I_D(PEAK)= • 1+

•









I

= I + 2 • Q

• f

1–D_MAX

Q(TOT)

Q

G(TOT)

= 3mA + 2 • 30nC • 300kHz = 21mA

1

2

0.4

2

1.5A

•





= • 1+

= 2.7A







P

DISS

= 24V • 21mA = 504mW



1– 0.669

T = 70°C + 504mW • 34°C/W = 87.1°C

J

The diode chosen for this application is the

MURS320T3H, manufactured by ON Semiconductor.

This surface mount diode has a maximum average

forwardcurrentof3Aat140°Candamaximumreverse

voltage of 200V. The maximum forward voltage drop

at 25°C is 0.875V and is 0.71V at 150°C (the positive

TC of the series resistance is compensated by the

negative TC of the diode forward voltage).

10. The inductor ripple current was chosen to be 40ꢀ

and the maximum load current is 1.5A. For a current

limit set at 30ꢀ above the maximum load current, the

maximum switch and sense resistor currents are:

1.3 •I_O(MAX)

1

n

χ

2





I_SW(MAX)= I_R(SENSE)= • 1+

•









1–D_MAX

1

2

0.4 1.3 •1.5A



2



= • 1+

•

= 3.5A









1– 0.669

The power dissipated by the diode is approximately:

P = I

D

• V

• (1 – D

)

D(PEAK)

F(PEAK)

MAX

11. The maximum current sense threshold for the

LTC3862-2is75mVatlowdutycycleandanormalized

slopegainof1.0.UsingFigure20,themaximumsense

voltage drops to 68mV at a duty cycle of 70ꢀ with a

normalized slope gain of 1, so the sense resistor is

calculated to be:

= 2.7A • 0.71V • (1 – 0.669) = 0.64W

14. Twotypesofoutputcapacitorsareconnectedinparal-

lel for this application; a low ESR ceramic capacitor

and an aluminum electrolytic for bulk storage. For

a 1ꢀ contribution to the total ripple voltage, the

maximum ESR of the composite output capacitance

is approximately:

V_SENSE(MAX)

68mV

3.5A

R_SENSE

=

= 19.4mΩ

I_SW(MAX)

0.01• V_OUT0.01• 72V

ESR_COUT

≤

=

= 0.267Ω

I_D(PEAK)

2.7A

For this application a 20mΩ, 1W surface mount resis-

tor was used for each phase.

38622f

34

LTC3862-2

applicaTions inForMaTion

Forthebulkcapacitance,whichweassumecontributes

1ꢀ to the total output ripple, the minimum required

capacitance is approximately:

2. In order to help dissipate the power from the MOS-

FETs and diodes, keep the ground plane on the layers

closest to the power components. Use power planes

for the MOSFETs and diodes in order to maximize the

heat spreading from these components into the PCB.

I_O(MAX)

0.01•n • V_OUT• f 0.01• 2 • 72V • 300kHz

= 3.45µF

1.5A

C_OUT

≥

=

3. Place all power components in a tight area. This will

minimize the size of high current loops. The high di/

dtloopsformedbythesenseresistor,powerMOSFET,

the boost diode and the output capacitor should be

kept as small as possible to avoid EMI.

For this application, in order to obtain both low ESR

and an adequate ripple current rating (see Figure 23),

two47μF, 100Valuminumelectrolyticcapacitorswere

connected in parallel with six 2.2μF, 100V ceramic

capacitors. Figure 26 illustrates the switching wave-

forms for this application circuit.

4. Orient the input and output capacitors and current

sense resistors in a way that minimizes the distance

between the pads connected to the ground plane.

Keep the capacitors for INTV_CC, 3V8 and V_INas close

as possible to LTC3862-2.

SW1

100V/DIV

5. Place the INTV_CCdecoupling capacitor as close as

possible to the INTV_CCand PGND pins, on the same

layer as the IC. A low ESR (X5R or better) 4.7μF to

10μF ceramic capacitor should be used.

I

L1

2A/DIV

SW2

100V/DIV

I

L2

2A/DIV

6. Use a local via to ground plane for all pads that

connect to the ground. Use multiple vias for power

components.

V

OUT

200mV/DIV

AC COUPLED

38622 F26

2µs/DIV

V

= 24V

IN

= 72V

OUT

7. Place the small-signal components away from high

frequency switching nodes on the board. The pinout

of the LTC3862-2 was carefully designed in order to

make component placement easy. All of the power

componentscanbeplacedononesideoftheIC, away

from all of the small-signal components.

I

= 0.6A

Figure 26. LTC3862-2 Switching Waveforms

for 72V Output Boost Converter

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the converter:

8. The exposed area on the bottom of the QFN package

is internally connected to PGND; however it should

not be used as the main path for high current flow.

1. Forlowerpowerapplicationsa2-layerPCboardissuf-

ficient. However, for higher power levels, a multilayer

PCboardisrecommended.Usingasolidgroundplane

and proper component placement under the circuit is

the easiest way to ensure that switching noise does

not affect the operation.

9. The MOSFETs should also be placed on the same

layeroftheboardasthesenseresistors.TheMOSFET

source should connect to the sense resistor using a

short, wide PCB trace.

38622f

35

LTC3862-2

applicaTions inForMaTion

10. The output resistor divider should be located as

close as possible to the IC, with the bottom resistor

connected between FB and SGND. The PCB trace

connecting the top resistor to the upper terminal of

the output capacitor should avoid any high frequency

switching nodes.

14. Keep the MOSFET drain nodes (SW1, SW2) away

from sensitive small-signal nodes, especially from

the opposite channel’s current-sensing signals. The

SW nodes can have slew rates in excess of 1V/ns

relative to ground and should therefore be kept on

the “output side” of the LTC3862-2.

11. Since the inductor acts like a current source in a peak

current mode control topology, its placement on the

board is less critical than the high di/dt components.

15. Check the stress on the power MOSFETs by indepen-

dentlymeasuringthedrain-to-sourcevoltagesdirectly

across the devices terminals. Beware of inductive

ringingthatcouldexceedthemaximumvoltagerating

of the MOSFET. If this ringing cannot be avoided and

exceeds the maximum rating of the device, choose

a higher voltage rated MOSFET or consider using a

snubber.

12. TheSENSE⁺andSENSE^–PCBtracesshouldberouted

parallel to one another with minimum spacing in be-

tween all the way to the sense resistor. These traces

should avoid any high frequency switching nodes in

the layout. These PCB traces should also be Kelvin-

connected to the interior of the sense resistor pads,

in order to avoid sensing errors due to parasitic PCB

resistance IR drops.

16. When synchronizing the LTC3862-2 to an external

clock, use a low impedance source such as a logic

gate to drive the SYNC pin and keep the lead as short

as possible.

13. If an external RC filter is used between the sense

resistorandtheSENSE⁺andSENSE^–pins, thesefilter

components should be placed as close as possible to

the SENSE⁺and SENSE^–pins of the IC. Ensure that

theSENSE^–lineisconnectedtothegroundonlyatthe

point where the current sense resistor is grounded.

38622f

36

LTC3862-2

Typical applicaTions

A 6V to 60V Input, 12V/6A Output 2-Phase SEPIC Application Circuit

Q3

V

L1

IN

PBSS9110T

6V TO 60V

VP5-0083-R

D3

1,2,3

•

4,5,6

•

V

OUT

R9

R5

PBZ6.8B

12V AT 6A

C

OUT7-8

220k

10k

+

C

OUT1-6

R12

56k

IN1-5

6× 6.8µF

50V

2× 150µF

16V

5× 2.2µF

100V

D4

BAS516

R27

22k

Q2

PMST5550

10,11,12

7,8,9

R13

10k

CD1-3

3 × 2.2µF

100V

V

OUT

Q5

PMST5550

D1

V8P10

R3

845k

C

U1

L2

VP5-0083-R

1µF

LTC3862-2

R11

D

V

IN

MAX

SLOPE

BLANK

249k

1,2,3

4,5,6

Q1

RUN

3V8

•

D2

BSC060N10NS3G

V8P10

3V8

R

C2

4.7µF

10Ω

C1

1nF

PHASEMODE INTV

CC

10,11,12

7,8,9

C

OSC

SS

CD4-6

3 × 2.2µF

100V

FREQ

SS

GATE1

10nF

C3

10nF

R6

0.004Ω

66.5k

+

SENSE1

R

C1

–

ITH

SENSE1

6.34k

C

C2

100pF

C

C1

10nF

FB

PGND

GATE2

NC

R1

12.4k

Q4

SGND

CLKOUT

SYNC

PLLFLTR

BSC060N10NS3G

R4

10Ω

R2

113k

+

V

SENSE2

OUT

–

C4

10nF

R8

0.004Ω

SENSE2

38621 TA02a

Start-Up

Load Step

RUN

5V/DIV

I

OUT

5A/DIV

V

OUT

5V/DIV

V

OUT

1V/DIV

I

+ I

L1A L1B

AC-COUPLED

10A/DIV

+ I

L2A L2B

10A/DIV

38622 TA04b

38622 TA04c

500µs/DIV

V

= 12V

OUT

= 12Ω

V

= 12V

IN

= 12V

V

= 12V

OUT

R

L

∆I

= 1A TO 6A

OUT

Efficiency

91

90

89

88

87

86

85

84

83

82

81

80

V

= 12V

OUT

V

= 6V

= 12V

= 14V

IN

100

1000

10000

LOAD CURRENT (mA)

38622 TA01b

38622f

37

LTC3862-2

Typical applicaTions

A 6V to 32V Input, 80V/7A Output 2-Phase Boost Converter Application Circuit

V

IN

L1

D1

V8P10

6V TO 32V

16µH

PQA2050-16

1nF

Q1

D

3V8

+

MAX

BSC06N10

10Ω

SENSE1

SLOPE

BLANK

10nF

3.3mΩ

100µF

–

100V

PHASEMODE

FREQ

SENSE1

RUN

+

6.8µF, 50V

110k

24.9k

0.1µF

V

100k

OUT

SS

80V

10nF

1µF

7A (MAX)

LTC3862-2

12k

100µF

100V

ITH

FB

V

IN

220pF

4.7µF

2.2µF

100V

×5

12.4k

INTV

CC

3.3mΩ

Q2

SGND

GATE1

PGND

10Ω

796k

V

OUT

GATE2

SENSE2

BSC06N10

–

CLKOUT

L2

16µH

PQA2050-16

10nF

D2

V8P10

SYNC

+

PLLFLTR

SENSE2

3862 TA03a

Start-Up

Efficiency vs Output Current

V

= 80V

97

95

93

91

89

87

85

83

81

79

77

OUT

RUN

5V/DIV

V

OUT

20V/DIV

I

L1

10A/DIV

I

L2

V

IN

V

IN

V

IN

V

IN

= 6V

= 9V

= 12V

= 24V

10A/DIV

38622 TA03b

2ms/DIV

V

OUT

R

= 12V

IN

V

= 80V

= 100Ω

L

10

100

1000

10000

LOAD CURRENT (mA)

38622 TA03c

38622f

38

LTC3862-2

Typical applicaTions

A 24V Input, 48V/6A Output 2-Phase Boost Converter Application Circuit

V

IN

L1

D1

30BQ060

8.5V TO 36V

19µH

PA2050-193

1nF

Q1

D

3V8

+

MAX

HAT2279H

10Ω

SENSE1

SLOPE

BLANK

0.005Ω

1W

10nF

100µF

35V

–

PHASEMODE

FREQ

SENSE1

RUN

+

22µF 25V

45.3k

24.9k

0.1µF

7.87k

22µF 25V

V

150k

OUT

SS

48V

4.7nF

1µF

6A (MAX)

LTC3862-2

30.1k

100µF

35V

10µF 50V

ITH

FB

V

IN

100pF

4.7µF

10µF 50V

INTV

CC

0.005Ω

1W

SGND

GATE1

PGND

10Ω

301k

V

OUT

Q2

HAT2279H

GATE2

SENSE2

–

CLKOUT

L2

19µH

PA2050-193

10nF

D2

30BQ060

SYNC

+

PLLFLTR

SENSE2

3862 TA04a

Start-Up

Load Step

RUN

5V/DIV

I

OUT

5A/DIV

I

L1

I

L1

5A/DIV

I

L2

I

L2

5A/DIV

V

OUT

1V/DIV

AC-COUPLED

V

OUT

50V/DIV

38622 TA04c

38622 TA04b

500µs/DIV

1ms/DIV

V

= 24V

V

= 24V

IN

OUT

IN

OUT

L

= 48V

∆I

OUT

= 1A TO 5A

R

= 100Ω

Efficiency

100

96

92

88

84

10000

V

= 24V

IN

OUT

= 48V

EFFICIENCY

POWER LOSS

1000

10000

100

1000

LOAD CURRENT (mA)

38622 TA04d

38622f

39

LTC3862-2

Typical applicaTions

A 24V Input, 107V/1.5A Output 2-Phase Boost Converter Application Circuit

V

IN

D1

PDS4150

8.5V TO 36V

L1

58µH

1nF

Q1

D

3V8

+

MAX

Si7430DP

10Ω

SENSE1

SLOPE

BLANK

0.010Ω

1W

10nF

–

PHASEMODE

FREQ

SENSE1

RUN

22µF 25V

68.1k

24.9k

100µF

150V

0.1µF

6.65k

22µF 25V

+

V

150k

OUT

SS

107V

2200pF

1µF

1.5A (MAX)

LTC3862-2

43.5k

8× 1µF 250V

ITH

FB

V

IN

47pF

4.7µF

INTV

CC

0.010Ω

1W

SGND

GATE1

PGND

10Ω

576k

V

OUT

Q2

Si743ODP

GATE2

–

SENSE2

CLKOUT

10nF

D2

PDS4150

SYNC

L2

58µH

+

PLLFLTR

SENSE2

38622 TA05a

L1, L2: CHAMPS TECHNOLOGIES HRPQA2050-57

PULSE ENGINEERING PA2050-583

Start-Up

Load Step

RUN

5V/DIV

I

OUT

2A/DIV

I

L1

I

2A/DIV

L1

2A/DIV

I

L2

2A/DIV

I

L2

2A/DIV

V

OUT

1V/DIV

AC-COUPLED

V

OUT

50V/DIV

38622 TA05c

38622 TA05b

500µs/DIV

= 500mA TO 1.5A

2ms/DIV

V

I

= 24V

OUT

LOAD

V

I

= 24V

IN

OUT

= 107V

= 400mA

LOAD

Efficiency

100

100000

V

= 24V

IN

OUT

= 107V

96

92

88

84

80

76

EFFICIENCY

10000

1000

POWER LOSS

10000

100

1000

LOAD CURRENT (mA)

38622 TA05d

38622f

40

LTC3862-2

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

FE Package

24-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663)

Exposed Pad Variation AA

7.70 – 7.90*

3.25

(.128)

(.303 – .311)

3.25

(.128)

24 23 22 21 20 19 18 17 16 15 14 13

6.60 ±0.10

4.50 ±0.10

2.74

(.108)

6.40

(.252)

BSC

2.74

(.108)

SEE NOTE 4

0.45 ±0.05

1.05 ±0.10

0.65 BSC

5

7

8

1

2

3

4

6

9 10 11 12

RECOMMENDED SOLDER PAD LAYOUT

1.20

(.047)

MAX

4.30 – 4.50*

(.169 – .177)

0.25

REF

0° – 8°

0.65

(.0256)

BSC

0.09 – 0.20

(.0035 – .0079)

0.50 – 0.75

(.020 – .030)

0.05 – 0.15

(.002 – .006)

0.195 – 0.30

FE24 (AA) TSSOP 0208 REV Ø

(.0077 – .0118)

TYP

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE

FOR EXPOSED PAD ATTACHMENT

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

MILLIMETERS

(INCHES)

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

38622f

41

LTC3862-2

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

GN Package

24-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.337 – .344*

(8.560 – 8.738)

.033

(0.838)

REF

24 23 22 21 20 19 18 17 16 15 1413

.045 ±.005

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.254 MIN

.150 – .165

1

2

3

4

5

6

7

8

9 10 11 12

.0165 ±.0015

.0250 BSC

RECOMMENDED SOLDER PAD LAYOUT

.015 ± .004

(0.38 ± 0.10)

.0532 – .0688

(1.35 – 1.75)

× 45°

.004 – .0098

(0.102 – 0.249)

.0075 – .0098

(0.19 – 0.25)

0° – 8° TYP

.016 – .050

(0.406 – 1.270)

.008 – .012

.0250

(0.635)

BSC

GN24 (SSOP) 0204

(0.203 – 0.305)

TYP

NOTE:

1. CONTROLLING DIMENSION: INCHES

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

3. DRAWING NOT TO SCALE

38622f

42

LTC3862-2

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

UH Package

24-Lead Plastic QFN (5mm × 5mm)

(Reference LTC DWG # 05-08-1747 Rev A)

0.75 ±0.05

5.40 ±0.05

3.90 ±0.05

3.20 ± 0.05

3.25 REF

3.20 ± 0.05

PACKAGE OUTLINE

0.30 ± 0.05

0.65 BSC

PIN 1 NOTCH

R = 0.30 TYP

OR 0.35 × 45°

CHAMFER

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

BOTTOM VIEW—EXPOSED PAD

R = 0.05

TYP

R = 0.150

TYP

0.75 ± 0.05

5.00 ± 0.10

23 24

0.00 – 0.05

0.55 ± 0.10

PIN 1

TOP MARK

(NOTE 6)

1

2

3.20 ± 0.10

5.00 ± 0.10

3.25 REF

3.20 ± 0.10

(UH24) QFN 0708 REV A

0.30 ± 0.05

0.200 REF

0.65 BSC

NOTE:

1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

38622f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

43

LTC3862-2

Typical applicaTion

A 6V to 60V, 12V/6A Output 2-Phase SEPIC Application Circuit

Q3

V

L1

IN

PBSS9110T

6V TO 60V

VP5-0083-R

D3

1,2,3

•

4,5,6

•

V

OUT

R9

R5

PBZ6.8B

12V AT 6A

C

OUT7-8

220k

10k

+

C

OUT1-6

R12

56k

IN1-5

6× 6.8µF

50V

2× 150µF

16V

5× 2.2µF

100V

D4

BAS516

R27

22k

Q2

PMST5550

10,11,12

7,8,9

R13

10k

CD1-3

3 × 2.2µF

100V

V

OUT

Q5

PMST5550

D1

V8P10

R3

845k

C

U1

L2

VP5-0083-R

1µF

LTC3862-2

R11

D

V

IN

MAX

SLOPE

BLANK

249k

1,2,3

4,5,6

Q1

RUN

3V8

•

D2

BSC060N10NS3G

V8P10

3V8

R

C2

4.7µF

10Ω

C1

1nF

PHASEMODE INTV

CC

10,11,12

7,8,9

C

OSC

SS

CD4-6

3 × 2.2µF

100V

FREQ

SS

GATE1

10nF

C3

10nF

R6

0.004Ω

66.5k

+

SENSE1

R

C1

–

ITH

SENSE1

6.34k

C

C2

100pF

C

C1

10nF

FB

PGND

GATE2

NC

R1

12.4k

Q4

SGND

CLKOUT

SYNC

PLLFLTR

BSC060N10NS3G

R4

10Ω

R2

113k

+

V

SENSE2

OUT

–

C4

10nF

R8

0.004Ω

SENSE2

38621 TA06

relaTeD parTs

PART NUMBER DESCRIPTION

COMMENTS

LTC3788/

LTC3788-1

Dual Output, Multiphase Synchronous Step-Up Controller 4.5V (Down to 2.5V After Start-Up) ≤ V ≤ 38V, V

Up to 60V,

OUT

IN

50kHz to 900kHz Fixed Frequency, 5mm × 5mm QFN-32, SSOP-28

LTC3787/

LTC3787-1

Single Output, Dual Channel Multiphase Synchronous

Step-Up Controller

4.5V (Down to 2.5V After Start-Up) ≤ V ≤ 38V, V

Up to 60V,

OUT

IN

50kHz to 900kHz Fixed Frequency, 4mm × 5mm QFN-28, SSOP-28

LTC3786

Low I Synchronous Step-Up Controller

4.5V (Down to 2.5V After Start-Up) ≤ V ≤ 38V, V Up to 60V,

Q

IN

OUT

50kHz to 900kHz Fixed Frequency, 3mm × 3mm QFN-32, MSOP-16E

LTC3862/

LTC3862-1

Multiphase, Dual Channel Single Output Current Mode

Step-Up DC/DC Controller

4V ≤ V ≤ 36V, 5V or 10V Gate Drive, 75kHz to 500kHz Fixed Operating

IN

Frequency, SSOP-24, TSSOP-24, 5mm × 5mm QFN-24

LTC3859A

Low I , Triple Output Buck/Buck/Boost Synchronous

All Outputs Remain in Regulation Through Cold Crank, 4.5V (Down to

Q

DC/DC Controller

2.5V After Start-Up) ≤ V ≤ 38V, V

Up to 24V, V

OUT(BOOST)

Up

IN

OUT(BUCKS)

to 60V, I = 55µA

Q

LTC3789

High Efficiency Synchronous 4-Switch Buck-Boost

DC/DC Controller

4V ≤ V ≤ 38V, 0.8V ≤ V

≤ 38V, 4mm × 5mm QFN-28, SSOP-28

IN

OUT

38622f

LT 0312 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

44

●

 LINEAR TECHNOLOGY CORPORATION 2012

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3789
厂家：	Linear Systems
描述：	Multi-Phase Current Mode Step-Up DC/DC Controller 多相电流模式升压型DC / DC控制器多相元件控制器
文件：	总44页 (文件大小：829K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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